External Memory Interface Handbook Volume 3: Reference Material

ID 683841
Date 7/24/2019
Public
Document Table of Contents

5.5.6. Bonding Interface Guidelines

Bonding allows a single data stream to be split between two memory controllers, providing the ability to expand the interface data width similar to a single 64-bit controller. This section provides some guidelines for setting up the bonding interface.

  1. Bonding interface ports are exported to the top level in your design. You should connect each bonding_in* port in one hard memory controller to the corresponding bonding_out_*port in the other hard memory controller, and vice versa.
  2. You should modify the Avalon signal connections to drive the bonding interface with a single user logic/master, as follows:
    1. AND both avl_ready signals from both hard memory controllers before the signals enter the user logic.
    2. AND both avl_rdata_valid signals from both hard memory controllers before the signals enter the user logic. (The avl_rdata_valid signals should be identical for both hard memory controllers.)
    3. Branch the following signals from the user logic to both hard memory controllers:
      • avl_burstbegin
      • avl_addr
      • avl_read_req
      • avl_write_req
      • avl_size
    4. Split the following signals according to each multi-port front end data port width:
      • avl_rdata
      • avl_wdata
      • avl_be

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