External Memory Interface Handbook Volume 3: Reference Material: For UniPHY-based Device Families

ID 683841
Date 3/06/2023
Public
Document Table of Contents

12.4. RLDRAM II Timing Diagrams

This topic contains timing diagrams for UniPHY-based external memory interface IP for RLDRAM protocols.

The following figures present timing diagrams, based on a Stratix III device:

Figure 83. Half-Rate RLDRAM II Read


Notes for the above Figure:

  1. Controller receives read command.
  2. Controller issues read command to PHY.
  3. PHY issues read command to memory.
  4. PHY receives read data from memory.
  5. Controller receives read data from PHY.
  6. User logic receives read data from controller.
Figure 84. Half-Rate RLDRAM II Write


Notes for the above Figure:

  1. Controller receives write command.
  2. Controller receives write data.
  3. Controller issues write command to PHY.
  4. PHY issues write command to memory.
  5. Controller sends write data to PHY.
  6. PHY sends write data to memory.
Figure 85. Full-Rate RLDRAM II Read


Notes for the above Figure:

  1. Controller receives read command.
  2. Controller issues read command to PHY.
  3. PHY issues read command to memory.
  4. PHY receives read data from memory.
  5. Controller receives read data from PHY.
  6. User logic receives read data from controller.
Figure 86. Full-Rate RLDRAM II Write


Notes for the above Figure:

  1. Controller receives write command.
  2. Controller receives write data.
  3. Controller issues write command to PHY.
  4. PHY issues write command to memory.
  5. Controller sends write data to PHY.
  6. PHY sends write data to memory.