External Memory Interface Handbook Volume 3: Reference Material

ID 683841
Date 7/24/2019
Public
Document Table of Contents

5. Functional Description—Hard Memory Interface

The hard (on-chip) memory interface components are available in the Arria V and Cyclone V device families.

The Arria V device family includes hard memory interface components supporting DDR2 and DDR3 SDRAM memory protocols at speeds of up to 533 MHz. For the Quartus II software version 12.0 and later, the Cyclone V device family supports both hard and soft interface support.

The Arria V device family supports both hard and soft interfaces for DDR3 and DDR2, and soft interfaces for LPDDR2 SDRAM, QDR II SRAM, and RLDRAM II memory protocols. The Cyclone V device family supports both hard and soft interfaces for DDR3, DDR2, and LPDDR2 SDRAM memory protocols.

The hard memory interface consists of three main parts, as follows:

  • The multi-port front end (MPFE), which allows multiple independent accesses to the hard memory controller.
  • The hard memory controller, which initializes, refreshes, manages, and communicates with the external memory device.
  • The hard PHY, which provides the physical layer interface to the external memory device.
Figure 143. Hard Memory Interface Architecture


Did you find the information on this page useful?

Characters remaining:

Feedback Message