External Memory Interface Handbook Volume 3: Reference Material: For UniPHY-based Device Families

ID 683841
Date 3/06/2023
Document Table of Contents
Give Feedback

13.6.4. Generating IP With the Debug Port

The following steps summarize the procedure for implementing your IP with the EMIF On-Chip Debug Port enabled.
  1. Start the Quartus Prime software and generate a new external memory interface. For QDR II and RLDRAM II protocols, ensure that sequencer optimization is set to Performance (for Nios II-based sequencer).
  2. On the Diagnostics tab of the parameter editor, turn on Enable EMIF On-Chip Debug Port.
  3. Ensure that the EMIF On-Chip Debug Port interface type is set to Avalon-MM Slave.
  4. Click Finish to generate your IP.
  5. Find the Avalon interface in the top-level generated file. Connect this interface to your debug component.
    input  wire [19:0] seq_debug_addr,        //    seq_debug.address
    input  wire        seq_debug_read_req,    //        .read
    output wire [31:0] seq_debug_rdata,       //        .readdata
    input  wire        seq_debug_write_req,   //        .write
    input  wire [31:0] seq_debug_wdata,       //        .writedata
    output wire        seq_debug_waitrequest, //        .waitrequest
    input  wire [3:0]  seq_debug_be,          //        .byteenable
    output wire        seq_debug_rdata_valid  //        .readdatavalid
    If you are using UniPHY-based IP with the hard memory controller, also connect the seq_debug_clk and seq_debug_reset_in signals to clock and asynchronous reset signals that control your debug logic.
  6. Find the core_debug.h and core_debug_defines.h header files in <design_name>/<design_name>_s0_software and include these files in your debug component code.
  7. Write your debug component using the supported command codes, to read and write to the Avalon-MM interface.
The debug data structure resides at the memory address SEQ_CORE_DEBUG_BASE, which is defined in the core_debug_defines.h header file.