External Memory Interface Handbook Volume 3: Reference Material

ID 683841
Date 7/24/2019
Public
Document Table of Contents

4.7. Sequencer Debug Information

Following calibration, the sequencer loads a set of debug information onto an output port. You can use the SignalTap II Logic Analyzer to access the debug information in the presynthesized design.

You could also bring this port to a register, to latch the value and make it accessible to a host processor.

The output port where the debug information is available is not normally connected to anything, so it could be removed during synthesis.

Signal name: phy_cal_debug_info

Module: <corename>_s0.v

The signal is 32 bits wide, and is defined in the following table.

Table 60.  Sequencer Debug Data
best_comp_result [23:16]

Best data comparison result on a per-pin basis from the Read-Write Manager. Pin 16 - 23.

Any mismatch on respective pin data comparison produces a high bit.

If calibration fails, the result is a non-zero value. When calibration passes, the result is zero.

best_comp_result [15:8]

Best data comparison result on a per-pin basis from the Read-Write Manager. Pin 8 - 15.

Any mismatch on respective pin data comparison produces a high bit.

If calibration fails, the result is a non-zero value. When calibration passes, the result is zero.

best_comp_result [7:0]

Best data comparison result on a per-pin basis from the Read-Write Manager. Pin 0 - 7.

Any mismatch on respective pin data comparison produces a high bit.

If calibration fails, the result is a non-zero value. When calibration passes, the result is zero.

margin [7:0]

Margin found by the sequencer if calibration passes. Number represents the amount of subsequent PLL phase where valid data is found.

If calibration fails, this number is zero. When calibration passes, this value is non-zero.

Debug Example and Interpretation

The following table illustrates possible debug signal values and their interpretations.

best_comp_result [23:16] best_comp_result [15:8] best_comp_result [7:0] margin [7:0]
Passing result 0000 0000 0000 0000 0000 0000 0001 0000
Interpretation No failing pins. No failing pins. No failing pins. 16 phases of margin for valid window. Ideal case for 300Mhz interface.
Failing result 0010 0000 1111 1111 0000 0000 0000 0000
Interpretation Pin 21 failing. All pins failing, pin 8-15. No failing pins. No valid window.

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