External Memory Interface Handbook Volume 3: Reference Material: For UniPHY-based Device Families

ID 683841
Date 3/06/2023
Document Table of Contents

3.5.2. Clock Domains

The hard PHY contains circuitry that uses the following clock domains:

AFI clock domain (pll_afi_clk) —The main full-rate clock signal that synchronizes most of the circuit logic.

Avalon® clock domain (pll_avl_clk) —Synchronizes data on the internal Avalon® bus, namely the Read/Write Manager, PHY Manager, and Data Manager data. The data is then transferred to the AFI clock domain. To ensure reliable data transfer between clock domains, the Avalon® clock period must be an integer multiple of the AFI clock period, and the phases of the two clocks must be aligned.

Address and Command clock domain (pll_addr_cmd_clk) —Synchronizes the global asychronous reset signal, used by the I/Os in this clock domain.