External Memory Interface Handbook Volume 3: Reference Material

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ID 683841
Date 7/24/2019
Public
Document Table of Contents

6.6.4.5.2. ECC Write Backs

If the controller ECC is enabled and a read operation results in a correctable ECC error, the controller corrects the location in memory, if write backs are enabled. The correction results in scheduling a new read-modify-write.

A new read is performed at the location to ensure that a write operation modifying the location is not overwritten. The actual ECC correction operation is performed as a read-modify-write operation. ECC write backs are enabled and disabled through the cfg_enable_ecc_code_overwrites field in the ctrlcfg register.

Note: Double-bit errors do not generate read-modify-write commands. Instead, double-bit error address and count are reported through the erraddr and dbecount registers, respectively. In addition, a double-bit error interrupt can be enabled through the dramintr register.

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