External Memory Interface Handbook Volume 3: Reference Material: For UniPHY-based Device Families

ID 683841
Date 3/06/2023
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3.4.2. Reset

The ports of the MPFE must connect to the same reset signal.

When the reset signal is asserted, it resets the command and data FIFO buffer in the MPFE without resetting the hard memory controller.

Note: The global_reset_n and soft_reset_n signals are asynchronous. You must include a false_path or relaxed delay timing exception in the project Synopsys Design Constraint File (.sdc) to avoid unnecessary recovery and removal analysis.

For easiest management of reset signals, Intel recommends the following sequence at power-up:

  1. Initially global_reset_n, soft_reset_n, and the MPFE reset signals are all asserted.
  2. global_reset_n is deasserted.
  3. Wait for pll_locked to transition high.
  4. soft_reset_n is deasserted.
  5. (Optional) If you encounter difficulties, wait for the controller signal local_cal_success to go high, indicating that the external memory interface has successfully completed calibration, before deasserting the MPFE FIFO reset signals. This will ensure that read/write activity cannot occur until the interface is successfully calibrated.