When the reset signal is asserted, it resets the command and data FIFO buffer in the MPFE without resetting the hard memory controller.
For easiest management of reset signals, Intel recommends the following sequence at power-up:
- Initially global_reset_n, soft_reset_n, and the MPFE reset signals are all asserted.
- global_reset_n is deasserted.
- Wait for pll_locked to transition high.
- soft_reset_n is deasserted.
- (Optional) If you encounter difficulties, wait for the controller signal local_cal_success to go high, indicating that the external memory interface has successfully completed calibration, before deasserting the MPFE FIFO reset signals. This will ensure that read/write activity cannot occur until the interface is successfully calibrated.
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