External Memory Interface Handbook Volume 3: Reference Material

ID 683841
Date 7/24/2019
Public
Document Table of Contents

4.5.3. Write Datapath

The write datapath is a static path and is timing analyzed to meet timing requirements.
Figure 139. Write Datapath


In the PHY write data path, for even write latency the write data valid, write data, and dqs enable pass through one stage of fr_cycle_shifter in a flow through path. For odd memory write latency, the output is shifted by a full-rate clock cycle. The full-rate cycle-shifted output feeds into a simple DDIO.

Figure 140. Write Datapath Timing Diagram


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