External Memory Interface Handbook Volume 3: Reference Material: For UniPHY-based Device Families

ID 683841
Date 3/06/2023
Document Table of Contents

2.5.3. Write Datapath

The write datapath is a static path and is timing analyzed to meet timing requirements.
Figure 34. Write Datapath

In the PHY write data path, for even write latency the write data valid, write data, and dqs enable pass through one stage of fr_cycle_shifter in a flow through path. For odd memory write latency, the output is shifted by a full-rate clock cycle. The full-rate cycle-shifted output feeds into a simple DDIO.

Figure 35. Write Datapath Timing Diagram