External Memory Interface Handbook Volume 3: Reference Material: For UniPHY-based Device Families

ID 683841
Date 3/06/2023
Document Table of Contents

4.7. SDRAM Power Management

The SDRAM controller subsystem supports the following power saving features in the SDRAM:
  • Partial array self‑refresh (PASR)
  • Power down
  • Deep power down for LPDDR2

To enable self-refresh for the memories of one or both chip selects, program the selfshreq bit and the sefrfshmask bit in the lowpwreq register.

Power-saving mode initiates either due to a user command or from inactivity. The number of idle clock cycles after which a memory can be put into power-down mode is programmed through the autopdycycles field of the lowpwrtiming register.

Power-down mode forces the SDRAM burst-scheduling bank-management logic to close all banks and issue the power down command. The SDRAM automatically reactivates when an active SDRAM command is received.

To enable deep power down request for the LPDDR2 memories of one or both chip selects, program the deeppwrdnreq bit and the deepwrdnmask field of the lowpwreq register.

Other power-down modes are performed only under user control.