12.3.2. Simulation Example Design
- An instance of the synthesis example design. As described in the previous section, the synthesis example design contains a traffic generator and an instance of the UniPHY memory interface. These blocks default to abstract simulation models where appropriate for rapid simulation.
- A memory model, which acts as a generic model that adheres to the memory protocol specifications. Frequently, memory vendors provide simulation models for specific memory components that you can download from their websites.
- A status checker, which monitors the status signals from the UniPHY IP and the traffic generator, to signal an overall pass or fail condition.
If you are using the Ping Pong PHY feature, the simulation example design includes two traffic generators issuing commands to two independent memory devices through two independent controllers and a common PHY, as shown in the following figure.
If you are using RLDRAM 3, the traffic generator in the simulation example design communicates directly with the PHY using AFI, as shown in the following figure.
You can obtain the simulation example design by generating your IP core. The files related to the simulation example design reside at < variation_name >_ example_design /simulation. After obtaining the generated files, you must still generate the simulation example design RTL for your desired HDL language. The file < variation_name >_ example_design /simulation/README.txt contains details about how to generate the IP and to run the simulation in ModelSim* or ModelSim* - Intel FPGA Edition.
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