External Memory Interface Handbook Volume 3: Reference Material

ID 683841
Date 7/24/2019
Public
Document Table of Contents

1.10. UniPHY Signals

The following tables list the UniPHY signals.
Table 3.  Clock and Reset Signals 

Name

Direction

Width

Description

pll_ref_clk

Input

1

PLL reference clock input.

global_reset_n

Input

1

Active low global reset for PLL and all logic in the PHY, which causes a complete reset of the whole system. Minimum recommended pulse width is 100ns.

soft_reset_n

Input

1

Holding soft_reset_n low holds the PHY in a reset state. However it does not reset the PLL, which keeps running. It also holds the afi_reset_n output low.

Table 4.  DDR2 and DDR3 SDRAM Interface Signals

Name

Direction

Width

Description

mem_ck, mem_ck_n

Output

MEM_CK_WIDTH

Memory clock.

mem_cke

Output

MEM_CLK_EN_WIDTH

Clock enable.

mem_cs_n

Output

MEM_CHIP_SELECT_WIDTH

Chip select..

mem_cas_n

Output

MEM_CONTROL_WIDTH

Column address strobe.

mem_ras_n

Output

MEM_CONTROL_WIDTH

Row address strobe.

mem_we_n

Output

MEM_CONTROL_WIDTH

Write enable.

mem_a

Output

MEM_ADDRESS_WIDTH

Address.

mem_ba

Output

MEM_BANK_ADDRESS_WIDTH

Bank address.

mem_dqs, mem_dqs_n

Bidirectional

MEM_DQS_WIDTH

Data strobe.

mem_dq

Bidirectional

MEM_DQ_WIDTH

Data.

mem_dm

Output

MEM_DM_WIDTH

Data mask.

mem_odt

Output

MEM_ODT_WIDTH

On-die termination.

mem_reset_n (DDR3 only)

Output

1

Reset

mem_ac_parity (DDR3 only, RDIMM/LRDIMM only)

Output

MEM_CONTROL_WIDTH

Address/command parity bit. (Even parity, per the RDIMM spec, JESD82-29A.)

mem_err_out_n (DDR3 only, RDIMM/LRDIMM only)

Input

MEM_CONTROL_WIDTH

Address/command parity error.

Table 5.  UniPHY Parameters

Parameter Name

Description

AFI_RATIO

AFI_RATIO is 1 in full-rate designs.

AFI_RATIO is 2 for half-rate designs.

AFI_RATIO is 4 for quarter-rate designs.

MEM_IF_DQS_WIDTH 

The number of DQS pins in the interface.

MEM_ADDRESS_WIDTH

The address width of the specified memory device.

MEM_BANK_WIDTH

The bank width of the specified memory device.

MEM_CHIP_SELECT_WIDTH

The chip select width of the specified memory device.

MEM_CONTROL_WIDTH

The control width of the specified memory device.

MEM_DM_WIDTH

The DM width of the specified memory device.

MEM_DQ_WIDTH

The DQ width of the specified memory device.

MEM_READ_DQS_WIDTH

The READ DQS width of the specified memory device.

MEM_WRITE_DQS_WIDTH

The WRITE DQS width of the specified memory device.

OCT_SERIES_TERM_CONTROL_WIDTH

OCT_PARALLEL_TERM_CONTROL_WIDTH

AFI_ADDRESS_WIDTH

The AFI address width, derived from the corresponding memory interface width.

AFI_BANK_WIDTH

The AFI bank width, derived from the corresponding memory interface width.

AFI_CHIP_SELECT_WIDTH

The AFI chip select width, derived from the corresponding memory interface width.

AFI_DATA_MASK_WIDTH

The AFI data mask width.

AFI_CONTROL_WIDTH

The AFI control width, derived from the corresponding memory interface width.

AFI_DATA_WIDTH

The AFI data width.

AFI_DQS_WIDTH

The AFI DQS width.

DLL_DELAY_CTRL_WIDTH

The DLL delay output control width.

NUM_SUBGROUP_PER_READ_DQS

A read datapath parameter for timing purposes.

QVLD_EXTRA_FLOP_STAGES

A read datapath parameter for timing purposes.

READ_VALID_TIMEOUT_WIDTH

A read datapath parameter; calibration fails when the timeout counter expires.

READ_VALID_FIFO_WRITE_ADDR_WIDTH

A read datapath parameter; the write address width for half-rate clocks.

READ_VALID_FIFO_READ_ADDR_WIDTH

A read datapath parameter; the read address width for full-rate clocks.

MAX_LATENCY_COUNT_WIDTH

A latency calibration parameter; the maximum latency count width.

MAX_READ_LATENCY

A latency calibration parameter; the maximum read latency.

READ_FIFO_READ_ADDR_WIDTH

READ_FIFO_WRITE_ADDR_WIDTH

MAX_WRITE_LATENCY_COUNT_WIDTH

A write datapath parameter; the maximum write latency count width.

INIT_COUNT_WIDTH

An initailization sequence.

MRSC_COUNT_WIDTH

A memory-specific initialization parameter.

INIT_NOP_COUNT_WIDTH

A memory-specific initialization parameter.

MRS_CONFIGURATION

A memory-specific initialization parameter.

MRS_BURST_LENGTH

A memory-specific initialization parameter.

MRS_ADDRESS_MODE

A memory-specific initialization parameter.

MRS_DLL_RESET

A memory-specific initialization parameter.

MRS_IMP_MATCHING

A memory-specific initialization parameter.

MRS_ODT_EN

A memory-specific initialization parameter.

MRS_BURST_LENGTH

A memory-specific initialization parameter.

MEM_T_WL

A memory-specific initialization parameter.

MEM_T_RL

A memory-specific initialization parameter.

SEQ_BURST_COUNT_WIDTH

The burst count width for the sequencer.

VCALIB_COUNT_WIDTH

The width of a counter that the sequencer uses.

DOUBLE_MEM_DQ_WIDTH

HALF_AFI_DATA_WIDTH

CALIB_REG_WIDTH

The width of the calibration status register.

NUM_AFI_RESET

The number of AFI resets to generate.

Note: For information about the AFI signals, refer to AFI 4.0 Specification in this chapter.

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