External Memory Interface Handbook Volume 3: Reference Material

ID 683841
Date 7/24/2019
Public
Document Table of Contents

7.5.1. Clock and Reset Signals

The following table lists the clock and reset signals.
Note: The suffix _n denotes active low signals.
Table 95.  Clock and Reset Signals

Name

Direction

Description

global_reset_n

Input

The asynchronous reset input to the controller. The IP core derives all other reset signals from resynchronized versions of this signal. This signal holds the PHY, including the PLL, in reset while low.

pll_ref_clk

Input

The reference clock input to PLL.

phy_clk

Output

The system clock that the PHY provides to the user. All user inputs to and outputs from the controller must be synchronous to this clock.

reset_phy_clk_n

Output

The reset signal that the PHY provides to the user. The IP core asserts reset_phy_clk_n asynchronously and deasserts synchronously to phy_clk clock domain.

aux_full_rate_clk

Output

An alternative clock that the PHY provides to the user. This clock always runs at the same frequency as the external memory interface. In half-rate designs, this clock is twice the frequency of the phy_clk and you can use it whenever you require a 2x clock. In full-rate designs, the same PLL output as the phy_clk signal drives this clock.

aux_half_rate_clk

Output

An alternative clock that the PHY provides to the user. This clock always runs at half the frequency as the external memory interface. In full-rate designs, this clock is half the frequency of the phy_clk and you can use it, for example to clock the user side of a half-rate bridge. In half-rate designs, or if the Enable Half Rate Bridge option is turned on. The same PLL output that drives the phy_clk signal drives this clock.

dll_reference_clk

Output

Reference clock to feed to an externally instantiated DLL.

reset_request_n

Output

Reset request output that indicates when the PLL outputs are not locked. Use this signal as a reset request input to any system‑level reset controller you may have. This signal is always low when the PLL is trying to lock, and so any reset logic using Intel advises you detect a reset request on a falling edge rather than by level detection.

soft_reset_n

Input

Edge detect reset input for control by other system reset logic. Assert to cause a complete reset to the PHY, but not to the PLL that the PHY uses.

seriesterminationcontrol

Input (for OCT slave)

Required signal for PHY to provide series termination calibration value. Must be connected to a user-instantiated OCT control block (alt_oct) or another UniPHY instance that is set to OCT master mode.

Output (for OCT master)

Unconnected PHY signal, available for sharing with another PHY.

parallelterminationcontrol

Input (for OCT slave)

Required signal for PHY to provide series termination calibration value. Must be connected to a user-instantiated OCT control block (alt_oct) or another UniPHY instance that is set to OCT master mode.

Output (for OCT master)

Unconnected PHY signal, available for sharing with another PHY.

oct_rdn

Input (for OCT master)

Must connect to calibration resistor tied to GND on the appropriate RDN pin on the device. (Refer to appropriate device handbook.)

oct_rup

Input (for OCT master)

Must connect to calibration resistor tied to Vccio on the appropriate RUP pin on the device. (See appropriate device handbook.)

dqs_delay_ctrl_import

Input

Allows the use of DLL in another PHY instance in this PHY instance. Connect the export port on the PHY instance with a DLL to the import port on the other PHY instance.

csr_clk

Output

Clock for the configuration and status register (CSR) interface, which is the same as afi_clk and is always synchronous relative to the main data slave interface.

Note:

  1. Applies only to the hard memory controller with multiport front end available in Arria V and Cyclone V devices.

Did you find the information on this page useful?

Characters remaining:

Feedback Message