External Memory Interface Handbook Volume 3: Reference Material

ID 683841
Date 7/24/2019
Public
Document Table of Contents

13.7.1. DDR2, DDR3, and LPDDR2 Resource Utilization in Arria V Devices

The following table shows typical resource usage of the DDR2, DDR3, and LPDDR2 SDRAM controllers with UniPHY in the current version of Quartus Prime software for Arria V devices.
Table 120.  Resource Utilization in Arria V Devices 

Protocol

Memory Width (Bits)

Combinational ALUTS

Logic Registers

M10K Blocks

Memory (Bits)

Hard Memory Controiler

Controller

DDR2 (Half rate)

8

2286

1404

4

6560

0

64

2304

1379

17

51360

0

DDR2 (Fullrate)

32

0

0

0

0

1

DDR3 (Half rate)

8

2355

1412

4

6560

0

64

2372

1440

17

51360

0

DDR3 (Full rate)

32

0

0

0

0

1

LPDDR2 (Half rate)

8

2230

1617

4

6560

0

32

2239

1600

10

25760

0

PHY

DDR2 (Half rate)

8

1652

2015

34

141312

0

64

1819

2089

34

174080

0

DDR2 (Fullrate)

32

1222

1415

34

157696

1

DDR3 (Half rate)

8

1653

1977

34

141312

0

64

1822

2090

34

174080

0

DDR3 (Full rate)

32

1220

1428

34

157696

0

LPDDR2 (Half rate)

8

2998

3187

35

150016

0

32

3289

3306

35

174592

0

Total

DDR2 (Half rate)

8

4555

3959

39

148384

0

64

4991

4002

52

225952

0

DDR2 (Fullrate)

32

1776

1890

35

158208

1

DDR3 (Half rate)

8

4640

3934

39

148384

0

64

5078

4072

52

225952

0

DDR3 (Full rate)

32

1774

1917

35

158208

1

LPDDR2 (Half rate)

8

5228

4804

39

156576

0

32

5528

4906

45

200352

0

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