External Memory Interface Handbook Volume 3: Reference Material: For UniPHY-based Device Families

ID 683841
Date 3/06/2023
Document Table of Contents

1.9. UniPHY Interfaces

The following figure shows the major blocks of the UniPHY and how it interfaces with the external memory device and the controller.
Note: Instantiating the delay-locked loop (DLL) and the phase-locked loop (PLL) on the same level as the UniPHY eases DLL and PLL sharing.
Figure 10. UniPHY Interfaces with the Controller and the External Memory

The following interfaces are on the UniPHY top-level file:

  • AFI
  • Memory interface
  • DLL sharing interface
  • PLL sharing interface
  • OCT interface


The UniPHY datapath uses the Altera PHY interface (AFI). The AFI is in a simple connection between the PHY and controller. The AFI is based on the DDR PHY interface (DFI) specification, with some calibration-related signals not used and some additional Intel® -specific sideband signals added.

For more information about the AFI, refer to AFI 3.0 Specification, in this chapter.

The Memory Interface

For information on the memory interface, refer to UniPHY Signals, in this chapter.

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