External Memory Interface Handbook Volume 3: Reference Material

ID 683841
Date 7/24/2019
Public
Document Table of Contents

7.5.6. Hard Controller Register Map

The hard controller register map allows you to control the hard memory controller settings.
Note: Dynamic reconfiguration is not currently supported.
The following table lists the register map for the hard controller.

Table 100.  Hard Controller Register Map

Address

Bit

Name

Default

Access

Description

0x000 3:0 CFG_CAS_WR_LAT 0 Read/Write Memory write latency.
0x001 4:0 CFG_ADD_LAT 0 Read/Write Memory additive latency.
0x002 4:0 CFG_TCL 0 Read/Write Memory read latency.
0x003 3:0 CFG_TRRD 0 Read/Write The activate to activate different banks timing parameter.
0x004 5:0 CFG_TFAW 0 Read/Write The four-activate window timing parameter.
0x005 7:0 CFG_TRFC 0 Read/Write The refresh cycle timing parameter.
0x006 12:0 CFG_TREFI 0 Read/Write The refresh interval timing parameter.
0x008 3:0 CFG_TREFI 0 Read/Write The activate to read/write timing parameter.
0x009 3:0 CFG_TRP 0 Read/Write The precharge to activate timing parameter.
0x00A 3:0 CFG_TWR 0 Read/Write The write recovery timing.
0x00B 3:0 CFG_TWTR 0 Read/Write The write to read timing parameter.
0x00C 3:0 CFG_TRTP 0 Read/Write The read to precharge timing parameter.
0x00D 4:0 CFG_TRAS 0 Read/Write The activate to precharge timing parameter.
0x00E 5:0 CFG_TRC 0 Read/Write The activate to activate timing parameter.
0x00F 15:0 CFG_AUTO_PD_CYCLES 0 Read/Write The number of idle clock cycles after which the controller should place the memory into power-down mode.
0x011 9:0 CFG_SELF_RFSH_EXIT_CYCLES 0 Read/Write The self-refresh exit cycles.
0x013 9:0 CFG_PDN_EXIT_CYCLES 0 Read/Write The power down exit cycles.
0x015 3:0 CFG_TMRD 0 Read/Write Mode register timing parameter.
0x016 4:0 CFG_COL_ADDR_WIDTH 0 Read/Write The number of column address bits for the memory devices in your memory interface.
0x017 4:0 CFG_ROW_ADDR_WIDTH 0 Read/Write The number of row address bits for the memory devices in your memory interface.
0x018 2:0 CFG_BANK_ADDR_WIDTH 0 Read/Write The number of bank address bits for the memory devices in your memory interface.
0x019 2:0 CFG_CS_ADDR_WIDTH 0 Read/Write The number of chip select address bits for the memory devices in your memory interface.
0x035 3:0 CFG_TCCD 0 Read/Write CAS#-to-CAS# command delay.
0x035 3:0 CFG_WRITE_ODT_CHIP 0 Read/Write CAS#-to-CAS# command delay.
0x037 3:0 CFG_READ_ODT_CHIP 0 Read/Write Read ODT Control.
0x040 2:0 CFG_TYPE 0 Read/Write Selects memory type.
7:3 CFG_BURST_LENGTH 0 Read/Write Configures burst length as a static decimal value.
9:8 CFG_ADDR_ORDER 0 Read/Write Address order selection.
10 CFG_ENABLE_ECC 0 Read/Write Enable the generation and checking of ECC.
11 CFG_ENABLE_AUTO_CORR 0 Read/Write Enable auto correction when single bit error is detected.
12 CFG_GEN_SBE 0 Read/Write When this bit equals 1, it enables the deliberate insertion of single-bit errors, bit 0, in the data written to memory. This bit is used only for testing purposes.
13 CFG_GEN_DBE 0 Read/Write When this bit equals 1, it enables the deliberate insertion of double-bit errors, bits 0 and 1, in the data written to memory. This bit is used only for testing purposes.
14 CFG_REORDER_DATA 0 Read/Write Enable Data Reordering.
15 CFG_USER_RFSH 0 Read/Write Enable User Refresh.
16 CFG_REGDIMM_ENABLE 0 Read/Write REG DIMM Configuration.
17 CFG_ENABLE_DQS_TRACKING 0 Read/Write Enable DQS Tracking.
18 CFG_OUTPUT_REGD 0 Read/Write Enable Registered Output.
19 CFG_ENABLE_NO_DM 0 Read/Write No Data Mask Configuration.
20 CFG_ENABLE_ECC_CODE_OVERWRITES 0 Read/Write Enable ECC Code Overwrite in Double Error Bit Detection.
0x043 7:0 CFG_INTERFACE_WIDTH 0 Read/Write Memory Interface Width.
0x044 3:0 CFG_DEVICE_WIDTH 0 Read/Write Memory Device Width.
0x045 0 CFG_CAL_REQ 0 Read/Write Request re-calibration.
6:1 CFG_CLOCK_OFF 0 Read/Write Disable memory clock.
0x047 0 STS_CAL_SUCCESS 0 Read Only Calibration Success.
1 STS_CAL_FAIL 0 Read Only Calibration Fail.
2 STS_SBE_ERROR 0 Read Only Single Bit Error Detected.
3 STS_DBE_ERROR 0 Read Only Double Bit Error Detected.
4 STS_CORR_DROPPED 0 Read Only Auto Correction Dropped.
0x048 0 CFG_ENABLE_INTR 0 Read/Write Enable Interrupt
1 CFG_MASK_SBE_INTR 0 Read/Write Mask Single Bit Error Interrupt.
2 CFG_MASK_DBE_INTR 0 Read/Write Mask Double Bit Error Interrupt.
3 CLEAR INTERRUPT 0 Write Clear Clear Interrupt.
0x049 7:0 STS_SBD_COUNT 0 Read Only Reports the number of SBE errors that have occurred since the status register counters were last cleared.
0x04A 7:0 STS_DBE_COUNT 0 Read Only Reports the number of SBE errors that have occurred since the status register counters were last cleared.
0x04B 31:0 STS_ERR_ADDR 0 Read Only The address of the most recent ECC error.
0x04F 0 CFG_MASK_CORR_DROPPED_INTR 0 Read/Write Auto Correction Dropped Count.
0x050 7:0 CFG_MASK_CORR_DROPPED_INTR 0 Read Only Auto Correction Dropped Count.
0x051 31:0 STS_CORR_DROPPED_ADDR 0 Read Only Auto Correction Dropped Address.
0x055 5:0 CFG_STARVE_LIMIT 0 Read/Write Starvation Limit.
0x056 1:0 CFG_MEM_BL 0 Read/Write Burst Length.
2 CFG_MEM_BL 0 Read/Write ECC Enable.
0x057 1:0 CFG_MEM_BL 0 Read/Write Specifies controller interface width.
0x058 11:0 CMD_PORT_WIDTH 0 Read/Write Specifies per command port data width.
0x05A 11:0 CMD_FIFO_MAP 0 Read/Write Specifies command port to Write FIFO association.
0x05C 11:0 CFG_CPORT_RFIFO_MAP 0 Read/Write Specifies command port to Read FIFO association.
23:12 CFG_RFIFO_CPORT_MAP 0 Read/Write Port assignment (0 - 5) associated with each of the N FIFO.
31:24 CFG_WFIFO_CPORT_MAP 0 Read/Write Port assignment (0 - 5) associated with each of the N FIFO. (con't)
0x05D 3:0 CFG_WFIFO_CPORT_MAP 0 Read/Write Port assignment (0 - 5) associated with each of the N FIFO.
14:4 CFG_CPORT_TYPE 0 Read/Write Command port type.
0x062 2:0 CFG_CLOSE_TO_FULL 0 Read/Write Indicates when the FIFO has this many empty entries left.
5:3 CFG_CLOSE_TO_EMPTY 0 Read/Write Indicates when the FIFO has this many valid entries left.
11:6 CFG_CLOSE_TO_EMPTY 0 Read/Write Port works in synchronous mode.
12 CFG_INC_SYNC 0 Read/Write Set the number of FF as clock synchronizer.
0x067 5:0 CFG_ENABLE_BONDING 0 Read/Write Enables bonding for each of the control ports.
7:6 CFG_DELAY_BONDING 0 Read/Write Set to the value used for the bonding input to bonding output delay.
0x069 5:0 CFG_AUTO_PCH_ENABLE 0 Read/Write Control auto-precharage options.
0x06A 17:0 MP_SCHEDULER_PRIORITY 0 Read/Write Set absolute user priority of the port
0x06D 29:0 RCFG_ST_WT 0 Read/Write Set static weight of the port.
31:30 RCFG_SUM_PRI_WT 0 Read/Write Set the sum of static weights for particular user priority.
0x06E 31:0 RCFG_SUM_PRI_WT 0 Read/Write Set the sum of static weights for particular user priority.
0x06F 29:0 RCFG_SUM_PRI_WT 0 Read/Write Set the sum of static weights for particular user priority.
0x0B9 0 CFG_DISABLE_MERGING 0 Read/Write Set to a one to disable command merging.

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