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1. Functional Description—UniPHY
2. Functional Description— Intel® Stratix® 10 EMIF IP
3. Functional Description— Intel® Arria® 10 EMIF IP
4. Functional Description— Intel® MAX® 10 EMIF IP
5. Functional Description—Hard Memory Interface
6. Functional Description—HPS Memory Controller
7. Functional Description—HPC II Controller
8. Functional Description—QDR II Controller
9. Functional Description—QDR-IV Controller
10. Functional Description—RLDRAM II Controller
11. Functional Description—RLDRAM 3 PHY-Only IP
12. Functional Description—Example Designs
13. Introduction to UniPHY IP
14. Latency for UniPHY IP
15. Timing Diagrams for UniPHY IP
16. External Memory Interface Debug Toolkit
17. Upgrading to UniPHY-based Controllers from ALTMEMPHY-based Controllers
1.1. I/O Pads
1.2. Reset and Clock Generation
1.3. Dedicated Clock Networks
1.4. Address and Command Datapath
1.5. Write Datapath
1.6. Read Datapath
1.7. Sequencer
1.8. Shadow Registers
1.9. UniPHY Interfaces
1.10. UniPHY Signals
1.11. PHY-to-Controller Interfaces
1.12. Using a Custom Controller
1.13. AFI 3.0 Specification
1.14. Register Maps
1.15. Ping Pong PHY
1.16. Efficiency Monitor and Protocol Checker
1.17. UniPHY Calibration Stages
1.18. Document Revision History
1.7.1.1. NIOS II-based Sequencer Function
1.7.1.2. Nios II-based Sequencer Architecture
1.7.1.3. Nios II-based Sequencer SCC Manager
1.7.1.4. NIOS II-based Sequencer RW Manager
1.7.1.5. NIOS II-based Sequencer PHY Manager
1.7.1.6. NIOS II-based Sequencer Data Manager
1.7.1.7. NIOS II-based Sequencer Tracking Manager
1.7.1.8. NIOS II-based Sequencer Processor
1.7.1.9. NIOS II-based Sequencer Calibration and Diagnostics
1.17.1. Calibration Overview
1.17.2. Calibration Stages
1.17.3. Memory Initialization
1.17.4. Stage 1: Read Calibration Part One—DQS Enable Calibration and DQ/DQS Centering
1.17.5. Stage 2: Write Calibration Part One
1.17.6. Stage 3: Write Calibration Part Two—DQ/DQS Centering
1.17.7. Stage 4: Read Calibration Part Two—Read Latency Minimization
1.17.8. Calibration Signals
1.17.9. Calibration Time
2.1. Stratix® 10 Supported Memory Protocols
2.2. Stratix® 10 EMIF IP Support for 3DS/TSV DDR4 Devices
2.3. Migrating to Stratix® 10 from Previous Device Families
2.4. Stratix® 10 EMIF Architecture: Introduction
2.5. Hardware Resource Sharing Among Multiple Stratix® 10 EMIFs
2.6. Stratix® 10 EMIF IP Component
2.7. Examples of External Memory Interface Implementations for DDR4
2.8. Stratix® 10 EMIF Sequencer
2.9. Stratix® 10 EMIF Calibration
2.10. Stratix 10 EMIF and SmartVID
2.11. Stratix® 10 Hard Memory Controller Rate Conversion Feature
2.12. Differences Between User-Requested Reset in Stratix® 10 versus Arria® 10
2.13. Compiling Stratix® 10 EMIF IP with the Quartus Prime Software
2.14. Debugging Stratix® 10 EMIF IP
2.15. Stratix® 10 EMIF for Hard Processor Subsystem
2.16. Stratix® 10 EMIF Ping Pong PHY
2.17. AFI 4.0 Specification
2.18. Stratix® 10 Resource Utilization
2.19. Stratix® 10 EMIF Latency
2.20. Integrating a Custom Controller with the Hard PHY
2.21. Document Revision History
2.4.1. Stratix® 10 EMIF Architecture: I/O Subsystem
2.4.2. Stratix® 10 EMIF Architecture: I/O Column
2.4.3. Stratix® 10 EMIF Architecture: I/O SSM
2.4.4. Stratix® 10 EMIF Architecture: I/O Bank
2.4.5. Stratix® 10 EMIF Architecture: I/O Lane
2.4.6. Stratix® 10 EMIF Architecture: Input DQS Clock Tree
2.4.7. Stratix® 10 EMIF Architecture: PHY Clock Tree
2.4.8. Stratix® 10 EMIF Architecture: PLL Reference Clock Networks
2.4.9. Stratix® 10 EMIF Architecture: Clock Phase Alignment
3.1. Supported Memory Protocols
3.2. Key Differences Compared to UniPHY IP and Previous Device Families
3.3. Migrating from Previous Device Families
3.4. Arria® 10 EMIF Architecture: Introduction
3.5. Hardware Resource Sharing Among Multiple EMIFs
3.6. Arria® 10 EMIF IP Component
3.7. Examples of External Memory Interface Implementations for DDR4
3.8. Arria® 10 EMIF Sequencer
3.9. Arria® 10 EMIF Calibration
3.10. Back-to-Back User-Controlled Refresh Usage in Arria® 10
3.11. Arria® 10 EMIF and SmartVID
3.12. Hard Memory Controller Rate Conversion Feature
3.13. Back-to-Back User-Controlled Refresh for Hard Memory Controller
3.14. Compiling Arria® 10 EMIF IP with the Quartus Prime Software
3.15. Debugging Arria® 10 EMIF IP
3.16. Arria® 10 EMIF for Hard Processor Subsystem
3.17. Arria® 10 EMIF Ping Pong PHY
3.18. AFI 4.0 Specification
3.19. Resource Utilization
3.20. Arria® 10 EMIF Latency
3.21. Arria® 10 EMIF Calibration Times
3.22. Integrating a Custom Controller with the Hard PHY
3.23. Memory Mapped Register (MMR) Tables
3.247.7. Document Revision History3.247.7. Document Revision History
3.4.1. Arria® 10 EMIF Architecture: I/O Subsystem
3.4.2. Arria® 10 EMIF Architecture: I/O Column
3.4.3. Arria® 10 EMIF Architecture: I/O AUX
3.4.4. Arria® 10 EMIF Architecture: I/O Bank
3.4.5. Arria® 10 EMIF Architecture: I/O Lane
3.4.6. Arria® 10 EMIF Architecture: Input DQS Clock Tree
3.4.7. Arria® 10 EMIF Architecture: PHY Clock Tree
3.4.8. Arria® 10 EMIF Architecture: PLL Reference Clock Networks
3.4.9. Arria® 10 EMIF Architecture: Clock Phase Alignment
3.23.1. ctrlcfg0: Controller Configuration
3.23.2. ctrlcfg1: Controller Configuration
3.23.3. ctrlcfg2: Controller Configuration
3.23.4. ctrlcfg3: Controller Configuration
3.23.5. ctrlcfg4: Controller Configuration
3.23.6. ctrlcfg5: Controller Configuration
3.23.7. ctrlcfg6: Controller Configuration
3.23.8. ctrlcfg7: Controller Configuration
3.23.9. ctrlcfg8: Controller Configuration
3.23.10. ctrlcfg9: Controller Configuration
3.23.11. dramtiming0: Timing Parameters
3.23.12. dramodt0: On-Die Termination Parameters
3.23.13. dramodt1: On-Die Termination Parameters
3.23.14. sbcfg0: Sideband Configuration
3.23.15. sbcfg1: Sideband Configuration
3.23.16. sbcfg2: Sideband Configuration
3.23.17. sbcfg3: Sideband Configuration
3.23.18. sbcfg4: Sideband Configuration
3.23.19. sbcfg5: Sideband Configuration
3.23.20. sbcfg6: Sideband Configuration
3.23.21. sbcfg7: Sideband Configuration
3.23.22. sbcfg8: Sideband Configuration
3.23.23. sbcfg9: Sideband Configuration
3.23.24. caltiming0: Command/Address/Latency Parameters
3.23.25. caltiming1: Command/Address/Latency Parameters
3.23.26. caltiming2: Command/Address/Latency Parameters
3.23.27. caltiming3: Command/Address/Latency Parameters
3.23.28. caltiming4: Command/Address/Latency Parameters
3.23.29. caltiming5: Command/Address/Latency Parameters
3.23.30. caltiming6: Command/Address/Latency Parameters
3.23.31. caltiming7: Command/Address/Latency Parameters
3.23.32. caltiming8: Command/Address/Latency Parameters
3.23.33. caltiming9: Command/Address/Latency Parameters
3.23.34. caltiming10: Command/Address/Latency Parameters
3.23.35. dramaddrw: Row/Column/Bank Address Width Configuration
3.23.36. sideband0: Sideband
3.23.37. sideband1: Sideband
3.23.38. sideband2: Sideband
3.23.39. sideband3: Sideband
3.23.40. sideband4: Sideband
3.23.41. sideband5: Sideband
3.23.42. sideband6: Sideband
3.23.43. sideband7: Sideband
3.23.44. sideband8: Sideband
3.23.45. sideband9: Sideband
3.23.46. sideband10: Sideband
3.23.47. sideband11: Sideband
3.23.48. sideband12: Sideband
3.23.49. sideband13: Sideband
3.23.50. sideband14: Sideband
3.23.51. sideband15: Sideband
3.23.52. dramsts: Calibration Status
3.23.53. ecc1: ECC General Configuration
3.23.54. ecc2: Width Configuration
3.23.55. ecc3: ECC Error and Interrupt Configuration
3.23.56. ecc4: Status and Error Information
3.23.57. ecc5: Address of Most Recent SBE/DBE
3.23.58. ecc6: Address of Most Recent Correct Command Dropped
6.1. Features of the SDRAM Controller Subsystem
6.2. SDRAM Controller Subsystem Block Diagram
6.3. SDRAM Controller Memory Options
6.4. SDRAM Controller Subsystem Interfaces
6.5. Memory Controller Architecture
6.6. Functional Description of the SDRAM Controller Subsystem
6.7. SDRAM Power Management
6.8. DDR PHY
6.9. Clocks
6.10. Resets
6.11. Port Mappings
6.12. Initialization
6.13. SDRAM Controller Subsystem Programming Model
6.14. Debugging HPS SDRAM in the Preloader
6.15. SDRAM Controller Address Map and Register Definitions
6.16. Document Revision History
13.7.1. DDR2, DDR3, and LPDDR2 Resource Utilization in Arria V Devices
13.7.2. DDR2 and DDR3 Resource Utilization in Arria II GZ Devices
13.7.3. DDR2 and DDR3 Resource Utilization in Stratix III Devices
13.7.4. DDR2 and DDR3 Resource Utilization in Stratix IV Devices
13.7.5. DDR2 and DDR3 Resource Utilization in Arria V GZ and Stratix V Devices
13.7.6. QDR II and QDR II+ Resource Utilization in Arria V Devices
13.7.7. QDR II and QDR II+ Resource Utilization in Arria II GX Devices
13.7.8. QDR II and QDR II+ Resource Utilization in Arria II GZ, Arria V GZ, Stratix III, Stratix IV, and Stratix V Devices
13.7.9. RLDRAM II Resource Utilization in Arria V Devices
13.7.10. RLDRAM II Resource Utilization in Arria II GZ, Arria V GZ, Stratix III, Stratix IV, and Stratix V Devices
16.1. User Interface
16.2. Setup and Use
16.3. Operational Considerations
16.4. Troubleshooting
16.5. Debug Report for Arria V and Cyclone V SoC Devices
16.6. On-Chip Debug Port for UniPHY-based EMIF IP
16.7. On-Chip Debug Port for Arria 10 EMIF IP
16.8. Driver Margining for Arria 10 EMIF IP
16.9. Read Setting and Apply Setting Commands for Arria 10 EMIF IP
16.10. Traffic Generator 2.0
16.11. The Traffic Generator 2.0 Report
16.12. Example Tcl Script for Running the EMIF Debug Toolkit
16.13. Calibration Adjustment Delay Step Sizes for Arria 10 Devices
16.14. Using the EMIF Debug Toolkit with Arria® 10 HPS Interfaces
16.15. Document Revision History
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7.5.6. Hard Controller Register Map
The hard controller register map allows you to control the hard memory controller settings.
Note: Dynamic reconfiguration is not currently supported.
The following table lists the register map for the hard controller.
Address |
Bit |
Name |
Default |
Access |
Description |
---|---|---|---|---|---|
0x000 | 3:0 | CFG_CAS_WR_LAT | 0 | Read/Write | Memory write latency. |
0x001 | 4:0 | CFG_ADD_LAT | 0 | Read/Write | Memory additive latency. |
0x002 | 4:0 | CFG_TCL | 0 | Read/Write | Memory read latency. |
0x003 | 3:0 | CFG_TRRD | 0 | Read/Write | The activate to activate different banks timing parameter. |
0x004 | 5:0 | CFG_TFAW | 0 | Read/Write | The four-activate window timing parameter. |
0x005 | 7:0 | CFG_TRFC | 0 | Read/Write | The refresh cycle timing parameter. |
0x006 | 12:0 | CFG_TREFI | 0 | Read/Write | The refresh interval timing parameter. |
0x008 | 3:0 | CFG_TREFI | 0 | Read/Write | The activate to read/write timing parameter. |
0x009 | 3:0 | CFG_TRP | 0 | Read/Write | The precharge to activate timing parameter. |
0x00A | 3:0 | CFG_TWR | 0 | Read/Write | The write recovery timing. |
0x00B | 3:0 | CFG_TWTR | 0 | Read/Write | The write to read timing parameter. |
0x00C | 3:0 | CFG_TRTP | 0 | Read/Write | The read to precharge timing parameter. |
0x00D | 4:0 | CFG_TRAS | 0 | Read/Write | The activate to precharge timing parameter. |
0x00E | 5:0 | CFG_TRC | 0 | Read/Write | The activate to activate timing parameter. |
0x00F | 15:0 | CFG_AUTO_PD_CYCLES | 0 | Read/Write | The number of idle clock cycles after which the controller should place the memory into power-down mode. |
0x011 | 9:0 | CFG_SELF_RFSH_EXIT_CYCLES | 0 | Read/Write | The self-refresh exit cycles. |
0x013 | 9:0 | CFG_PDN_EXIT_CYCLES | 0 | Read/Write | The power down exit cycles. |
0x015 | 3:0 | CFG_TMRD | 0 | Read/Write | Mode register timing parameter. |
0x016 | 4:0 | CFG_COL_ADDR_WIDTH | 0 | Read/Write | The number of column address bits for the memory devices in your memory interface. |
0x017 | 4:0 | CFG_ROW_ADDR_WIDTH | 0 | Read/Write | The number of row address bits for the memory devices in your memory interface. |
0x018 | 2:0 | CFG_BANK_ADDR_WIDTH | 0 | Read/Write | The number of bank address bits for the memory devices in your memory interface. |
0x019 | 2:0 | CFG_CS_ADDR_WIDTH | 0 | Read/Write | The number of chip select address bits for the memory devices in your memory interface. |
0x035 | 3:0 | CFG_TCCD | 0 | Read/Write | CAS#-to-CAS# command delay. |
0x035 | 3:0 | CFG_WRITE_ODT_CHIP | 0 | Read/Write | CAS#-to-CAS# command delay. |
0x037 | 3:0 | CFG_READ_ODT_CHIP | 0 | Read/Write | Read ODT Control. |
0x040 | 2:0 | CFG_TYPE | 0 | Read/Write | Selects memory type. |
7:3 | CFG_BURST_LENGTH | 0 | Read/Write | Configures burst length as a static decimal value. | |
9:8 | CFG_ADDR_ORDER | 0 | Read/Write | Address order selection. | |
10 | CFG_ENABLE_ECC | 0 | Read/Write | Enable the generation and checking of ECC. | |
11 | CFG_ENABLE_AUTO_CORR | 0 | Read/Write | Enable auto correction when single bit error is detected. | |
12 | CFG_GEN_SBE | 0 | Read/Write | When this bit equals 1, it enables the deliberate insertion of single-bit errors, bit 0, in the data written to memory. This bit is used only for testing purposes. | |
13 | CFG_GEN_DBE | 0 | Read/Write | When this bit equals 1, it enables the deliberate insertion of double-bit errors, bits 0 and 1, in the data written to memory. This bit is used only for testing purposes. | |
14 | CFG_REORDER_DATA | 0 | Read/Write | Enable Data Reordering. | |
15 | CFG_USER_RFSH | 0 | Read/Write | Enable User Refresh. | |
16 | CFG_REGDIMM_ENABLE | 0 | Read/Write | REG DIMM Configuration. | |
17 | CFG_ENABLE_DQS_TRACKING | 0 | Read/Write | Enable DQS Tracking. | |
18 | CFG_OUTPUT_REGD | 0 | Read/Write | Enable Registered Output. | |
19 | CFG_ENABLE_NO_DM | 0 | Read/Write | No Data Mask Configuration. | |
20 | CFG_ENABLE_ECC_CODE_OVERWRITES | 0 | Read/Write | Enable ECC Code Overwrite in Double Error Bit Detection. | |
0x043 | 7:0 | CFG_INTERFACE_WIDTH | 0 | Read/Write | Memory Interface Width. |
0x044 | 3:0 | CFG_DEVICE_WIDTH | 0 | Read/Write | Memory Device Width. |
0x045 | 0 | CFG_CAL_REQ | 0 | Read/Write | Request re-calibration. |
6:1 | CFG_CLOCK_OFF | 0 | Read/Write | Disable memory clock. | |
0x047 | 0 | STS_CAL_SUCCESS | 0 | Read Only | Calibration Success. |
1 | STS_CAL_FAIL | 0 | Read Only | Calibration Fail. | |
2 | STS_SBE_ERROR | 0 | Read Only | Single Bit Error Detected. | |
3 | STS_DBE_ERROR | 0 | Read Only | Double Bit Error Detected. | |
4 | STS_CORR_DROPPED | 0 | Read Only | Auto Correction Dropped. | |
0x048 | 0 | CFG_ENABLE_INTR | 0 | Read/Write | Enable Interrupt |
1 | CFG_MASK_SBE_INTR | 0 | Read/Write | Mask Single Bit Error Interrupt. | |
2 | CFG_MASK_DBE_INTR | 0 | Read/Write | Mask Double Bit Error Interrupt. | |
3 | CLEAR INTERRUPT | 0 | Write Clear | Clear Interrupt. | |
0x049 | 7:0 | STS_SBD_COUNT | 0 | Read Only | Reports the number of SBE errors that have occurred since the status register counters were last cleared. |
0x04A | 7:0 | STS_DBE_COUNT | 0 | Read Only | Reports the number of SBE errors that have occurred since the status register counters were last cleared. |
0x04B | 31:0 | STS_ERR_ADDR | 0 | Read Only | The address of the most recent ECC error. |
0x04F | 0 | CFG_MASK_CORR_DROPPED_INTR | 0 | Read/Write | Auto Correction Dropped Count. |
0x050 | 7:0 | CFG_MASK_CORR_DROPPED_INTR | 0 | Read Only | Auto Correction Dropped Count. |
0x051 | 31:0 | STS_CORR_DROPPED_ADDR | 0 | Read Only | Auto Correction Dropped Address. |
0x055 | 5:0 | CFG_STARVE_LIMIT | 0 | Read/Write | Starvation Limit. |
0x056 | 1:0 | CFG_MEM_BL | 0 | Read/Write | Burst Length. |
2 | CFG_MEM_BL | 0 | Read/Write | ECC Enable. | |
0x057 | 1:0 | CFG_MEM_BL | 0 | Read/Write | Specifies controller interface width. |
0x058 | 11:0 | CMD_PORT_WIDTH | 0 | Read/Write | Specifies per command port data width. |
0x05A | 11:0 | CMD_FIFO_MAP | 0 | Read/Write | Specifies command port to Write FIFO association. |
0x05C | 11:0 | CFG_CPORT_RFIFO_MAP | 0 | Read/Write | Specifies command port to Read FIFO association. |
23:12 | CFG_RFIFO_CPORT_MAP | 0 | Read/Write | Port assignment (0 - 5) associated with each of the N FIFO. | |
31:24 | CFG_WFIFO_CPORT_MAP | 0 | Read/Write | Port assignment (0 - 5) associated with each of the N FIFO. (con't) | |
0x05D | 3:0 | CFG_WFIFO_CPORT_MAP | 0 | Read/Write | Port assignment (0 - 5) associated with each of the N FIFO. |
14:4 | CFG_CPORT_TYPE | 0 | Read/Write | Command port type. | |
0x062 | 2:0 | CFG_CLOSE_TO_FULL | 0 | Read/Write | Indicates when the FIFO has this many empty entries left. |
5:3 | CFG_CLOSE_TO_EMPTY | 0 | Read/Write | Indicates when the FIFO has this many valid entries left. | |
11:6 | CFG_CLOSE_TO_EMPTY | 0 | Read/Write | Port works in synchronous mode. | |
12 | CFG_INC_SYNC | 0 | Read/Write | Set the number of FF as clock synchronizer. | |
0x067 | 5:0 | CFG_ENABLE_BONDING | 0 | Read/Write | Enables bonding for each of the control ports. |
7:6 | CFG_DELAY_BONDING | 0 | Read/Write | Set to the value used for the bonding input to bonding output delay. | |
0x069 | 5:0 | CFG_AUTO_PCH_ENABLE | 0 | Read/Write | Control auto-precharage options. |
0x06A | 17:0 | MP_SCHEDULER_PRIORITY | 0 | Read/Write | Set absolute user priority of the port |
0x06D | 29:0 | RCFG_ST_WT | 0 | Read/Write | Set static weight of the port. |
31:30 | RCFG_SUM_PRI_WT | 0 | Read/Write | Set the sum of static weights for particular user priority. | |
0x06E | 31:0 | RCFG_SUM_PRI_WT | 0 | Read/Write | Set the sum of static weights for particular user priority. |
0x06F | 29:0 | RCFG_SUM_PRI_WT | 0 | Read/Write | Set the sum of static weights for particular user priority. |
0x0B9 | 0 | CFG_DISABLE_MERGING | 0 | Read/Write | Set to a one to disable command merging. |
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