External Memory Interface Handbook Volume 3: Reference Material

ID 683841
Date 7/24/2019
Public
Document Table of Contents

15.6. RLDRAM 3 Timing Diagrams

This topic contains timing diagrams for UniPHY-based external memory interface IP for RLDRAM 3 protocols.
Figure 203. Quarter-Rate RLDRAM 3 Read


Notes for the above Figure:

  1. Controller issues read command to PHY.
  2. PHY issues read command to memory.
  3. PHY receives data from memory.
  4. Controller receives read data from PHY.
Figure 204. Quarter-Rate RLDRAM 3 Write


Notes for the above Figure:

  1. Controller issues write command to PHY.
  2. Data ready from controller for PHY.
  3. PHY issues write command to memory.
  4. PHY sends read data to memory.
Figure 205. Half-rate RLDRAM 3 Read


Notes for the above Figure:

  1. Controller issues read command to PHY.
  2. PHY issues read command to memory.
  3. PHY receives data from memory.
  4. Controller receives read data from PHY.
Figure 206. Half-Rate RLDRAM 3 Write


Notes for the above Figure:

  1. Controller issues write command to PHY.
  2. Data ready from controller for PHY.
  3. PHY issues write command to memory.
  4. PHY sends read data to memory.

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