External Memory Interface Handbook Volume 3: Reference Material: For UniPHY-based Device Families

ID 683841
Date 3/06/2023
Document Table of Contents

1.7. Sequencer

The sequencer initializes and calibrates the external memory interface. Depending on the combination of protocol and IP architecture in your external memory interface, you may have either an RTL-based sequencer or a Nios® II-based sequencer.

RTL-based sequencer implementations and Nios II-based sequencer implementations can have different pin requirements. You may not be able to migrate from an RTL-based sequencer to a Nios II-based sequencer and maintain the same pinout.

For information on sequencer support for different protocol-architecture combinations, refer to Introduction to Intel® FPGA Memory Solutions in Volume 1 of this handbook. For information on pin planning, refer to Planning Pin and FPGA Resources in Volume 2 of this handbook.