External Memory Interface Handbook Volume 3: Reference Material

ID 683841
Date 7/24/2019
Public
Document Table of Contents

7.5.4. CSR Interface Signals

The following table lists the CSR interface signals.
Table 98.  CSR Interface Signals

Signal Name

Direction

Description

csr_addr[]

Input

Register map address.The width of csr_addr is 16 bits.

csr_be[] 

Input

Byte-enable signal, which you use to mask off individual bytes during writes. csr_be is active high.

csr_clk    (1)
                           
                        

Output

Clock for the configuration and status register (CSR) interface, which is the same as afi_clk and is always synchronous relative to the main data slave interface.

csr_wdata[] 

Input

Write data bus. The width of csr_wdata is 32 bits.

csr_write_req 

Input

Write request signal. You cannot assert csr_write_req and csr_read_req signals at the same time.

csr_read_req

Input

Read request signal. You cannot assert csr_read_req and csr_write_req signals at the same time.

csr_rdata[] 

Output

Read data bus. The width of csr_rdata is 32 bits.

csr_rdata_valid 

Output

Read data valid signal. The csr_rdata_valid signal indicates that valid data is present on the read data bus.

csr_waitrequest

Output

The csr_waitrequest signal indicates that the HPC II is busy and not ready to accept request signals. If the csr_waitrequest signal goes high in the clock cycle when a read or write request is asserted, that request is not accepted. If the csr_waitrequest signal goes low, the HPC II is then ready to accept more requests.

Note to Table:

  1. Applies only to the hard memory controller with multiport front end available in Arria V and Cyclone V devices.

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