7.4.1. Clock and Reset Interface
The controller can have up to two clock domains, which are synchronous to each other. The controller operates with a single clock domain when there is no integrated half-rate bridge, and with two-clock domains when there is an integrated half-rate bridge. The clocks are provided by UniPHY.
The main controller clock is afi_clk, and the optional half-rate controller clock is afi_half_clk. The main and half-rate clocks must be synchronous and have a 2:1 frequency ratio. The optional quarter-rate controller clock is afi_quarter_clk, which must also be synchronous and have a 4:1 frequency ratio.
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