External Memory Interface Handbook Volume 3: Reference Material: For UniPHY-based Device Families

ID 683841
Date 3/06/2023
Document Table of Contents Creating a Top-Level File and Adding Constraints

This topic describes adding your Platform Designer (Standard) system to your top-level design and adding constraints to your design.
  1. Add your Platform Designer (Standard) system to your top-level design.
  2. Add the Intel® Quartus® Prime IP files (.qip) generated in step 2, to your Intel® Quartus® Prime project.
  3. Perform analysis and synthesis on your design.
  4. Constrain your EMIF design by running the <variation_name>_p0_pin_assignments.tcl pin constraints script.
  5. Add other necessary constraints—such as timing constraints, location assignments, and pin I/O standard assignments—for your design.
  6. Compile your design to generate an SRAM object file (.sof) and the hardware handoff files necessary for creating a preloader image.
    Note: You must regenerate the hardware handoff files whenever the HPS configuration changes; for example, due to changes in Peripheral Pin Multiplexing or I/O standard for HPS pins.

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