External Memory Interface Handbook Volume 3: Reference Material

ID 683841
Date 7/24/2019
Public
Document Table of Contents

1.14. Register Maps

The following table lists the overall register mapping for the DDR2, DDR3, and LPDDR2 SDRAM Controllers with UniPHY.
Note: Addresses shown in the table are 32-bit word addresses. If a byte-addressed master such as a Nios II processor accesses the CSR, it is necessary to multiply the addresses by four.
Table 15.  Register Map

Address

Description

UniPHY Register Map

0x001

Reserved.

0x004

UniPHY status register 0.

0x005

UniPHY status register 1.

0x006

UniPHY status register 2.

0x007

UniPHY memory initialization parameters register 0.

Controller Register Map

0x100

Reserved.

0x110

Controller status and configuration register.

0x120

Memory address size register 0.

0x121

Memory address size register 1.

0x122

Memory address size register 2.

0x123

Memory timing parameters register 0.

0x124

Memory timing parameters register 1.

0x125

Memory timing parameters register 2.

0x126

Memory timing parameters register 3.

0x130

ECC control register.

0x131

ECC status register.

0x132

ECC error address register.

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