External Memory Interface Handbook Volume 3: Reference Material: For UniPHY-based Device Families

ID 683841
Date 3/06/2023
Document Table of Contents

5.7. Document Revision History

Date Version Changes
March 2023 2023.03.06 In the Local Interface Signals topic, added a sentence to the description of the avl_be signal.
May 2017 2017.05.08 Rebranded as Intel.
October 2016 2016.10.31 Maintenance release.
May 2016 2016.05.02 Maintenance release.
November 2015 2015.11.02
  • Changed instances of Quartus II to Quartus Prime.
  • Added CFG_GEN_SBE and CFG_GEN_DBE to Hard Controller Register Map table.
May 2015 2015.05.04 Maintenance release.
December 2014 2014.12.15
  • Renamed Controller Register Map to Soft Controller Register Map.
  • Added Hard Controller Register Map.
August 2014 2014.08.15
  • Added "asynchronous" to descriptions of mp_cmd_reset_n_#_reset_n, mp_rfifo_reset_n_#_reset_n, and mp_wfifo_reset_n_#_reset_n signals in the MPFE Signals table.
  • Added Reset description to Hard Memory Controller section.
  • Added full-rate hard memory controller information for Arria V and Cyclone V to description of avl_addr[] in the Local Interface Signals table.
  • Reworded avl_burstbegin description in the Local Interface Signals table.
December 2013 2013.12.16
  • Removed references to ALTMEMPHY.
  • Removed references to SOPC Builder.
  • Removed Half-Rate Bridge information.
  • Modified Burst Merging description.
  • Expanded description of avl_ready in Local Interface Signals table.
  • Added descriptions of local_cal_success and local_cal_fail to Local Interface Signals table.
  • Modified description of avl_size in Local Interface Signals table.
  • Added guidance to initialize memory before use.
November 2012 2.1
  • Added Controller Register Map information.
  • Added Burst Merging information.
  • Updated User-Controlled Refresh Interface information.
  • Changed chapter number from 4 to 5.
June 2012 2.0
  • Added LPDDR2 support.
  • Added Feedback icon.
November 2011 1.1
  • Revised Figure 5–1.
  • Added AXI to Avalon-ST Converter information.
  • Added AXI Data Slave Interface information.
  • Added Half-Rate Bridge information.