External Memory Interface Handbook Volume 3: Reference Material

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ID 683841
Date 7/24/2019
Public
Document Table of Contents

1.9.2. The OCT Sharing Interface

By default, the UniPHY IP generates the required OCT control block at the top-level RTL file for the PHY.

If you want, you can instantiate this block elsewhere in your code and feed the required termination control signals into the IP core by turning off Master for OCT Control Block on the PHY Settings tab. If you turn off Master for OCT Control Block, you must instantiate the OCT control block or use another UniPHY instance as a master, and ensure that the parallel and series termination control bus signals are connected to the PHY.

The following figures show the PHY architecture with and without Master for OCT Control Block.

Figure 11. PHY Architecture with Master for OCT Control Block


Figure 12. PHY Architecture without Master for OCT Control Block


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