External Memory Interface Handbook Volume 3: Reference Material

ID 683841
Date 7/24/2019
Public
Document Table of Contents

1.14.1. UniPHY Register Map

The UniPHY register map allows you to control the memory components’ mode register settings. The following table lists the register map for UniPHY.
Note: Addresses shown in the table are 32-bit word addresses. If a byte-addressed master such as a Nios II processor accesses the CSR, it is necessary to multiply the addresses by four.
Table 16.  UniPHY Register Map

Address

Bit

Name

Default

Access

Description

0x001

15:0

Reserved.

0

Reserved for future use.

31:16

Reserved.

0

Reserved for future use.

0x002

15:0

Reserved.

0

Reserved for future use.

31:16

Reserved.

0

Reserved for future use.

0x004

0

SOFT_RESET

Write only

Initiate a soft reset of the interface. This bit is automatically deasserted after reset.

23:1

Reserved.

0

Reserved for future use.

24

AFI_CAL_SUCCESS

Read only

Reports the value of the UniPHY afi_cal_success. Writing to this bit has no effect.

25

AFI_CAL_FAIL

Read only

Reports the value of the UniPHY afi_cal_fail. Writing to this bit has no effect.

26

PLL_LOCKED

Read only

Reports the PLL lock status.

31:27

Reserved.

0

Reserved for future use.

0x005

7:0

Reserved.

0

Reserved for future use.

15:8

Reserved.

0

Reserved for future use.

23:16

Reserved.

0

Reserved for future use.

31:24

Reserved.

0

Reserved for future use.

0x006

7:0

INIT_FAILING_STAGE

Read only

Initial failing error stage of calibration. Only applicable if AFI_CAL_FAIL=1.

0: None

1: Read Calibration - VFIFO

2: Write Calibration - Write Leveling

3: Read Calibration - LFIFO Calibration

4: Write Calibration - Write Deskew

5: Unused

6: Refresh

7: Calibration Skipped

8: Calibration Aborted

9: Read Calibration - VFIFO After Writes

15:8

INIT_FAILING_SUBSTAGE

Read only

Initial failing error substage of calibration. Only applicable if AFI_CAL_FAIL=1.

If INIT_FAILING_STAGE = 1 or 9:

1: Read Calibration - Guaranteed read failure

2: Read Calibration - No working DQSen phase found

3: Read Calibration - Per-bit read deskew failure

If INIT_FAILING_STAGE = 2:

1: Write Calibration - No first working write leveling phase found

2: Write Calibration - No last working write leveling phase found

3: Write Calibration - Write leveling copy failure

If INIT_FAILING_STAGE = other, substages do not apply.

23:16

INIT_FAILING_GROUP

Read only

Initial failing error group of calibration. Only applicable if AFI_CAL_FAIL=1.

Returns failing DQ pin instead of failing group, if:

INIT_FAILING_STAGE=1 and INIT_FAILING_SUBSTAGE=3.

Or

INIT_FAILING_STAGE=4 and INIT_FAILING_SUBSTAGE=1.

31:24

Reserved.

0

Reserved for future use.

0x007

31:0

DQS_DETECT

Read only

Identifies if DQS edges have been identified for each of the groups. Each bit corresponds to one DQS group.

0x008(DDR2)

1:0

RTT_NOM

Read only

Rtt (nominal) setting of the DDR2 Extended Mode Register used during memory initialization.

31:2

Reserved.

0

Reserved for future use.

0x008(DDR3)

2:0

RTT_NOM

Rtt (nominal) setting of the DDR3 MR1 mode register used during memory initialization.

4:3

Reserved.

0

Reserved for future use.

6:5

ODS

Output driver impedence control setting of the DDR3 MR1 mode register used during memory initialization.

8:7

Reserved.

0

Reserved for future use.

10:9

RTT_WR

Rtt (writes) setting of the DDR3 MR2 mode register used during memory initialization.

31:11

Reserved.

0

Reserved for future use.

0x008(LPDDR2)

3:0

DS

Driver impedence control for MR3 during initialization.

31:4

Reserved.

Reserved for future use.

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