4.6.1. Read Calibration
Capture Clock and VFIFO Calibration
A VFIFO buffer is a FIFO buffer that is calibrated to reflect the read latency of the interface. The calibration process selects the correct read pointer of the FIFO. The VFIFO function delays the controller's afi_rdata_valid signal to align to data captured internally to the PHY. LFIFO buffers are FIFO buffers which ensure that data from different DQS groups arrives at the user side at the same time. Calibration ensures that data arrives at the user side with minimal latency.
Capture clock and VFIFO calibration performs the following steps:
- Executes a guaranteed write routine in the read-write (RW) manager.
- Sweeps VFIFO buffer values, beginning at 0, in the PHY Manager.
- For each adjustment of the VFIFO buffer, sweeps the capture clock phase in the PLL Manager to find the first phase that works. This is accomplished by issuing a read to the RW Manager and performing a bit check. Data is compared for all data bits.
- Increments the capture clock phase in the PLL Manager until capture clock phase values are exhausted or until the system stops working. If there are no more capture clock phase values to try, calibration increments the VFIFO buffer value in the PHY Manager, and phase sweep again until the system stops working.
Completion of this step establishes a working range of values.
- As a final step, calibration centers the capture clock phase within the working range.
Read Latency Tuning
Read latency tuning performs the following steps to achieve the optimal latency value:
- Assigns one LFIFO buffer for each DQ group.
- Aligns read data to the AFI clock.
- Gradually reduces LFIFO latency until reads fail, then increases latency to find the minimum value that yields reliable operation.
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