External Memory Interface Handbook Volume 3: Reference Material

ID 683841
Date 7/24/2019
Public
Document Table of Contents

6.4.4. FPGA-to-HPS SDRAM Interface

The FPGA-to-HPS SDRAM interface provides masters implemented in the FPGA fabric access to the SDRAM controller subsystem in the HPS. The interface has three port types that are used to construct the following AXI or Avalon-MM interfaces:

  • Command ports—issue read and/or write commands, and for receive write acknowledge responses
  • 64‑bit read data ports—receive data returned from a memory read
  • 64‑bit write data ports—transmit write data

The FPGA‑to‑HPS SDRAM interface supports six command ports, allowing up to six Avalon-MM interfaces or three AXI interfaces. Each command port can be used to implement either a read or write command port for AXI, or be used as part of an Avalon-MM interface. The AXI and Avalon-MM interfaces can be configured to support 32‑, 64‑, 128‑, and 256‑bit data.

Table 65.  FPGA-to-HPS SDRAM Controller Port Types 

Port Type

Available Number of Ports

Command

6

64‑bit read data

4

64‑bit write data

4

The FPGA‑to‑HPS SDRAM controller interface can be configured with the following characteristics:

  • Avalon-MM interfaces and AXI interfaces can be mixed and matched as required by the fabric logic, within the bounds of the number of ports provided to the fabric.
  • Because the AXI protocol allows simultaneous read and write commands to be issued, two SDRAM control ports are required to form an AXI interface.
  • Because the data ports are natively 64-bit, they must be combined if wider data paths are required for the interface.
  • Each Avalon-MM or AXI interface of the FPGA‑to‑HPS SDRAM interface operates on an independent clock domain.
  • The FPGA‑to‑HPS SDRAM interfaces are configured during FPGA configuration.

The following table shows the number of ports needed to configure different bus protocols, based on type and data width.

Table 66.  FPGA-to-HPS SDRAM Port Utilization 

Bus Protocol

Command Ports

Read Data Ports

Write Data Ports

32‑ or 64‑bit AXI

2

1

1

128‑bit AXI

2

2

2

256‑bit AXI

2

4

4

32‑ or 64‑bit Avalon-MM

1

1

1

128‑bit Avalon-MM

1

2

2

256‑bit Avalon-MM

1

4

4

32‑ or 64‑bit Avalon-MM write‑only

1

0

1

128‑bit Avalon-MM write‑only

1

0

2

256‑bit Avalon-MM write‑only

1

0

4

32‑ or 64‑bit Avalon-MM read‑only

1

1

0

128‑bit Avalon-MM read‑only

1

2

0

256‑bit Avalon-MM read‑only

1

4

0

 

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