External Memory Interface Handbook Volume 3: Reference Material

ID 683841
Date 7/24/2019
Public
Document Table of Contents

7.4.6. Controller External Interfaces

The following table lists the controller’s external interfaces.
Table 94.  Summary of Controller External Interfaces 

Interface Name

Display Name

Type

Description

Clock and Reset Interface

Clock and Reset Interface

Clock and Reset Interface

AFI  (1)

Clock and reset generated by UniPHY to the controller.

Avalon-ST Data Slave Interface

Command Channel

Avalon-ST Data Slave Interface

Avalon-ST  (2)

Address and command channel for read and write, single command single data (SCSD).

Write Data Channel

Avalon-ST Data Slave Interface

Avalon-ST  (2)

Write Data Channel, single command multiple data (SCMD).

Read Data Channel

Avalon-ST Data Slave Interface

Avalon-ST  (2)

Read data channel, SCMD with read data error response.

Controller-PHY Interface

AFI 4.0

AFI Interface

AFI  (1)

Interface between controller and PHY.

Memory Side-Band Signals

Self Refresh (Low Power) Interface

Self Refresh (Low Power) Interface

Avalon Control & Status Interface  (2)

SDRAM-specific signals to place memory into low-power mode.

User-Controller Refresh Interface

User-Controller Refresh Interface

Avalon Control & Status Interface  (2)

SDRAM-specific signals to request memory refresh.

Configuration and Status Register (CSR) Interface

CSR

Configuration and Status Register Interface

Avalon-MM  (2)

Enables on-the-fly configuration of memory timing parameters, address widths, and controller behaviour.

Notes:

  1. For information about AFI signals, refer to AFI 4.0 Specification in the Functional Description - UniPHY chapter.
  2. For information about Avalon signals, refer to Avalon Interface Specifications.

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