External Memory Interface Handbook Volume 3: Reference Material

ID 683841
Date 7/24/2019
Public
Document Table of Contents

14.6. RLDRAM 3 Latency

The following table shows the latency in full-rate memory clock cycles.

Table 135.  RLDRAM 3 Latency (In Full-Rate Memory Clock Cycles)

Latency in Full-Rate Memory Clock Cycles

Rate

PHY Address & Command

Memory Maximum Read

PHY Read Return

Controller Read Return

Round Trip

Round Trip Without Memory

Quarter

7

3–16

18

0

28–41

25

Half

4

3–16

6

0

13–26

10

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