External Memory Interface Handbook Volume 3: Reference Material

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ID 683841
Date 7/24/2019
Public
Document Table of Contents

2.19. Stratix® 10 EMIF Latency

The following latency data applies to all memory protocols supported by the Stratix® 10 EMIF IP.

Table 39.  Latency in Full-Rate Memory Clock Cycles
Rate 1 Controller Address & Command PHY Address & Command Memory Read Latency 2 PHY Read Data Return Controller Read Data Return Round Trip Round Trip Without Memory
Half:Write 12 2 3-23
Half:Read 8 2 3-23 6 8 27-47 24
Quarter:Write 14 2 3-23
Quarter:Read 10 2 3-23 6 14 35-55 32
Half:Write (ECC) 14 2 3-23
Half:Read (ECC) 12 2 3-23 6 8 31-51 28
Quarter:Write (ECC) 14 2 3-23
Quarter:Read (ECC) 12 2 3-23 6 14 37-57 34
  1. User interface rate; the controller always operates in half rate.
  2. Minimum and maximum read latency range for DDR3, DDR4, and LPDDR3.

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