2.11. Stratix® 10 Hard Memory Controller Rate Conversion Feature
To facilitate timing closure, you may choose to clock your core user logic at quarter-rate, resulting in easier timing closure at the expense of increased area and latency. To improve efficiency and help reduce overall latency, you can run the hard memory controller and PHY at half rate.
The rate conversion feature converts traffic from the FPGA core to the hard memory controller from quarter-rate to half-rate, and traffic from the hard memory controller to the FPGA core from half-rate to quarter-rate. From the perspective of user logic inside the FPGA core, the effect is the same as if the hard memory controller were running at quarter-rate.
The rate conversion feature is enabled automatically during IP generation whenever all of the following conditions are met:
- The hard memory controller is in use.
- User logic runs at quarter-rate.
- The interface targets either an ES2 or production device.
- Running the hard memory controller at half-rate dpoes not exceed the fMax specification of the hard memory controller and hard PHY.
When the rate conversion feature is enabled, you should see the following info message displayed in the IP generation GUI:PHY and controller running at 2x the frequency of user logic for improved efficiency.
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