External Memory Interface Handbook Volume 3: Reference Material: For UniPHY-based Device Families

ID 683841
Date 3/06/2023
Document Table of Contents

2.9. Stratix® 10 EMIF Calibration

The calibration process compensates for skews and delays in the external memory interface.

The following effects can be compensated for by the calibration process:

  • Timing and electrical constraints, such as setup/hold time and Vref variations.
  • Circuit board and package factors, such as skew, fly-by effects, and manufacturing variations.
  • Environmental uncertainties, such as variations in voltage and temperature.
  • The demanding effects of small margins associated with high-speed operation.
Note: The calibration process is intended to maximize margins for robust EMIF operation; it cannot compensate for an inadequate PCB layout.