External Memory Interface Handbook Volume 3: Reference Material: For UniPHY-based Device Families

ID 683841
Date 3/06/2023
Document Table of Contents

2.12. Differences Between User-Requested Reset in Stratix® 10 versus Arria® 10

The following table highlights differences between the user-requested reset mechanism in the Arria® 10 EMIF IP and the Stratix® 10 EMIF IP.
Table 27.  
  Arria 10 Stratix 10
Reset-related signals global_reset_n



When can user logic request a reset? Any time after the FPGA enters user mode.

local_reset_req has effect only local_reset_done is high.

After device power-on, the local_reset_done signal transitions high upon completion of the first calibration, whether the calibration is successful or not.

Is user-requested reset a requirement? A user-requested reset is typically required to ensure the memory interface begins from a known state.

A user-requested reset is optional. The IOSSM (which is part of the device’s CNOC) automatically ensures that the memory interface begins from a known state as part of the device power-on sequence. A user-requested reset is necessarily only if the user logic must explicitly reset a memory interface after the device power-on sequence.

When does a user-requested reset actually happen? As soon as global_reset_n is driven low by user logic.

A reset request is handled by the IOSSM. If the IOSSM receives a reset request from multiple interfaces within the same I/O column, it must serialize the reset sequence of the individual interfaces. You should avoid making assumptions on when the reset sequence will begin after a request is issued.

Timing requirement and triggering mechanism. global_reset_n is an asynchronous, active-low reset signal. Reset assertion and de-assertion is level-triggered.

Reset request is sent by transitioning the local_reset_req signal from low to high, then keeping the signal at the high state for a minimum of 2 EMIF core clock cycles, then transitioning the signal from high to low. local_reset_req is asynchronous in that there is no setup/hold timing to meet, but it must meet the minimum pulse width requirement of 2 EMIF core clock cycles.

How long can an external memory interface be kept in reset? The interface is kept in reset for as long as global_reset_n is driven low.

It is not possible to keep an external memory interface in reset indefinitely. Asserting local_reset_req high continuously has no effect as a reset request is completed by a full 0->1->0 pulse.

Delaying initial calibration. Initial calibration can be delayed for as long as desired by driving global_reset_n immediately after FPGA power-up.

Initial calibration cannot be skipped. The local_reset_done signal is driven high only after initial calibration has completed.

Reset scope (within an external memory interface). All circuits involved in EMIF operations are reset.

Only circuits that are required to restore EMIF to power-up state are reset. Excluded from the reset sequence are the IOSSM, the IOPLL(s), the DLL(s), and the CPA.

Reset scope (within an I/O column). global_reset_n is a column-wide reset. It is not possible to reset a subset of the memory interfaces within an I/O column.

local_reset_req is a per-interface reset.