External Memory Interface Handbook Volume 3: Reference Material: For UniPHY-based Device Families

ID 683841
Date 3/06/2023
Document Table of Contents

2.15. Stratix® 10 EMIF for Hard Processor Subsystem

The Stratix® 10 EMIF IP can enable the Stratix® 10 Hard Processor Subsystem (HPS) to access external DRAM memory devices.

To enable connectivity between the Stratix® 10 HPS and the Stratix® 10 EMIF IP, you must create and configure an instance of the Stratix® 10 External Memory Interface for HPS IP core, and use Qsys to connect it to the Stratix® 10 Hard Processor Subsystem instance in your system.

Supported Modes

The Stratix® 10 Hard Processor Subsystem is compatible with the following external memory configurations:

Protocol DDR3, DDR4, LPDDR3
Maximum memory clock frequency

DDR3: 1.067 GHz

DDR4: 1.333 GHz

LPDDR3: 800 MHz

Configuration Hard PHY with hard memory controller
Clock rate of PHY and hard memory controller Half-rate
Data width (without ECC) 16-bit, 32-bit, 64-bit
Data width (with ECC) 24-bit, 40-bit, 72-bit
DQ width per group x8
Maximum number of I/O lanes for address/command 3
Memory format Discrete, UDIMM, SODIMM, RDIMM
Ranks / CS# width Up to 2