External Memory Interface Handbook Volume 3: Reference Material

ID 683841
Date 7/24/2019
Document Table of Contents

2.15.1. Restrictions on I/O Bank Usage for Stratix® 10 EMIF IP with HPS

You can use only certain Stratix® 10 I/O banks to implement Stratix® 10 EMIF IP with the Stratix® 10 Hard Processor Subsystem.

The restrictions on I/O bank usage result from the Stratix® 10 HPS having hard-wired connections to the EMIF circuits in the I/O banks closest to the HPS. For any given EMIF configuration, the pin-out of the EMIF-to-HPS interface is fixed.

The following diagram illustrates the use of I/O banks and lanes for various EMIF-HPS data widths:

Figure 55.  Stratix® 10 External Memory Interfaces I/O Bank and Lanes Usage

The HPS EMIF uses the closest located external memory interfaces I/O banks to connect to SDRAM. These banks include:

  • Bank 2N—used for data I/Os (Data bits 31:0)
  • Bank 2M—used for address, command and ECC data I/Os
  • Bank 2L—used for data I/Os (Data bits 63:32)

If no HPS EMIF is used in a system, the entire HPS EMIF bank can be used as FPGA GPIO. If there is a HPS EMIF in a system, the unused HPS EMIF pins can be used as FPGA general I/O with restrictions:

  • Bank 2M:
    • Lane 3 is used for SDRAM ECC data. Unused pins in lane 3 can be used as FPGA inputs only.
    • Lanes 2, 1, and 0 are used for SDRAM address and command. Unused pins in these lanes can be used as FPGA inputs or outputs.
  • Bank 2N and Bank 2L :
    • Lanes 3, 2, 1, and 0 are used for data bits.
    • With 64-bit data widths, unused pins in these banks can be used as FPGA inputs only.
    • With 32-bit data widths, unused pins in Bank 2N can be used as FPGA inputs only.Unused pins for Bank 2L can be used as FPGA inputs or outputs.
    • With 16-bit data widths, Quartus® Prime assigns lane 0 and lane 1 as data lanes in bank 2N. Unused pins in lane 0 and lane 1 can be used as FPGA inputs only. The other two lanes are available to use as FPGA inputs or outputs.

By default, the Stratix® 10 External Memory Interface for HPS IP core together with the Quartus® Prime Fitter automatically implement the correct pin-out for HPS EMIF without you having to apply additional constraints. If you must modify the default pin-out for any reason, you must adhere to the following requirements, which are specific to HPS EMIF:

  1. Within a single data lane (which implements a single x8 DQS group):
    • DQ pins must use pins at indices 1, 2, 3, 6, 7, 8, 9, 10. You may swap the locations between the DQ bits (that is, you may swap location of DQ[0] and DQ[3]) so long as the resulting pin-out uses pins at these indices only.
    • DM/DBI pin must use pin at index 11. There is no flexibility.
    • DQS/DQS# must use pins at index 4 and 5. There is no flexibility.
  2. Assignment of data lanes must be as illustrated in the above figure. You are allowed to swap the locations of entire byte lanes (that is, you may swap locations of byte 0 and byte 3) so long as the resulting pin-out uses only the lanes permitted by your HPS EMIF configuration, as shown in the above figure.
  3. You must not change placement of the address and command pins from the default.
  4. You may place the alert# pin at any available pin location in either a data lane or an address and command lane.

To override the default generated pin assignments, comment out the relevant HPS_LOCATION assignments in the .qip file, and add your own location assignments (using set_location_assignment) in the .qsf file.

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