External Memory Interface Handbook Volume 3: Reference Material: For UniPHY-based Device Families

ID 683841
Date 3/06/2023
Document Table of Contents

2.6. Stratix® 10 EMIF IP Component

The external memory interface IP component for Stratix® 10 provides a complete solution for implementing external memory interfaces. The EMIF IP also includes a protocol-specific calibration algorithm that automatically determines the optimal delay settings for a robust external memory interface.

The external memory interface IP comprises the following parts:

  • A set of synthesizable files that you can integrate into a larger design
  • A stand-alone synthesizable example design that you can use for hardware validation
  • A set of simulation files that you can incorporate into a larger project
  • A stand-alone simulation example project that you can use to observe controller and PHY operation
  • A set of timing scripts that you can use to determine the maximum operating frequency of the memory interface based on external factors such as board skew, trace delays, and memory component timing parameters
  • A customized data sheet specific to your memory interface configuration