External Memory Interface Handbook Volume 3: Reference Material

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ID 683841
Date 7/24/2019
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Document Table of Contents

2.6.4. Clock Domains

The Stratix® 10 EMIF IP core provides a single clock domain to drive all logic connected to the EMIF core.

The frequency of the clock depends on the core-clock to memory-clock interface rate ratio. For example, a quarter-rate interface with an 800 MHz memory clock would provide a 200 MHz clock to the core (800 MHz / 4 = 200 MHz). The EMIF IP dynamically adjusts the phase of the core clock with respect to the periphery clock to maintain the optimum alignment for transferring data between the core and periphery. Independent EMIF IP cores driven from the same reference clock have independent core clock domains. You should employ one of the following strategies if you are implementing multiple EMIF cores:

  1. Treat all crossing between independent EMIF-generated clock domains as asynchronous, even though they are generated from the same reference clock.
  2. Use the Core clock sharing option to enforce that multiple EMIF cores share the same core clock. You must enable this option before IP generation. This option is applicable only for cores that reside in the same I/O column.

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