External Memory Interface Handbook Volume 3: Reference Material

ID 683841
Date 7/24/2019
Public
Document Table of Contents

2.6.2. File Sets

The Stratix® 10 EMIF IP core generates four output file sets for every EMIF IP core, arranged according to the following directory structure.
Table 25.  Generated File Sets
Directory Description
<core_name>/*

This directory contains only the files required to integrate a generated EMIF core into a larger design. This directory contains:

  • Synthesizable HDL source files
  • Customized TCL timing scripts specific to the core (protocol and topology)
  • HEX files used by the calibration algorithm to identify the interface parameters
  • A customized data sheet that describes the operation of the generated core
Note: The top-level HDL file is generated in the root folder as <core_name>.v (or <core_name .vhd> for VHDL designs). You can reopen this file in the parameter editor if you want to modify the EMIF core parameters and regenerate the design.
<core_name>_sim/*

This directory contains the simulation fileset for the generated EMIF core. These files can be integrated into a larger simulation project. For convenience, simulation scripts for compiling the core are provided in the /mentor, /cadence, /synopsys, and /riviera subdirectories.

The top-level HDL file, <core_name>.v (or <core_name>.vhd) is located in this folder, and all remaining HDL files are placed in the /altera_emif_arch_nf subfolder, with the customized data sheet. The contents of this directory are not intended for synthesis.

emif_<instance_num>_example_design/*

This directory contains a set of TCL scripts, QSYS project files and README files for the complete synthesis and simulation example designs. You can invoke these scripts to generate a standalone fully-synthesizable project complete with an example driver, or a standalone simulation design complete with an example driver and a memory model.

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