Product Discontinuance Notification
1. About the RapidIO II Intel® FPGA IP
2. Getting Started
3. Parameter Settings
4. Functional Description
5. Signals
6. Software Interface
7. Testbench
8. RapidIO II IP Core User Guide Archives
9. Document Revision History for the RapidIO II Intel® FPGA IP User Guide
A. Initialization Sequence
B. Differences Between RapidIO II IP Core and RapidIO IP Core
2.1. Installing and Licensing Intel® FPGA IP Cores
2.2. Intel® FPGA IP Evaluation Mode
2.32.4. Generating IP Cores2.32.4. Generating IP Cores
2.32.4. Generating IP Cores2.32.4. Generating IP Cores
2.5. RapidIO II IP Core Testbench Files
2.6. Simulating IP Cores
2.7. Integrating Your IP Core in Your Design
2.8. Compiling the Full Design and Programming the FPGA
2.9. Instantiating Multiple RapidIO II IP Cores in V-series FPGA devices
3.4.1. Device Identity CAR
3.4.2. Device Information CAR
3.4.3. Assembly Identity CAR
3.4.4. Assembly Information CAR
3.4.5. Processing Element Features CAR
3.4.6. Switch Port Information CAR
3.4.7. Switch Route Table Destination ID Limit CAR
3.4.8. Data Streaming Information CAR
3.4.9. Source Operations CAR
3.4.10. Destination Operations CAR
4.3.3.1. Maintenance Interface Transactions
4.3.3.2. Maintenance Interface Signals
4.3.3.3. Initiating MAINTENANCE Read and Write Transactions
4.3.3.4. Defining the Maintenance Address Translation Windows
4.3.3.5. Responding to MAINTENANCE Read and Write Requests
4.3.3.6. Handling Port-Write Transactions
4.3.3.7. Maintenance Interface Transaction Examples
4.3.3.8. Maintenance Packet Error Handling
4.3.5.3.1. User Sending Write Request
4.3.5.3.2. User Receiving Write Request
4.3.5.3.3. User Sending Read Request and Receiving Read Response
4.3.5.3.4. User Receiving Read Request and Sending Read Response
4.3.5.3.5. User Sending Streaming Write Request
4.3.5.3.6. User Receiving Streaming Write Request
6.1.1. CAR Memory Map
6.1.2. CSR Memory Map
6.1.3. LP-Serial Extended Features Block Memory Map
6.1.4. LP-Serial Lane Extended Features Block Memory Map
6.1.5. Error Management Extensions Extended Features Block Memory Map
6.1.6. Maintenance Module Registers Memory Map
6.1.7. I/O Logical Layer Master Module Registers Memory Map
6.1.8. I/O Logical Layer Slave Module Registers Memory Map
6.1.9. Doorbell Module Registers Memory Map
6.2.1.1. LP-Serial Register Block Header
6.2.1.2. Port Link Time-out Control CSR
6.2.1.3. Port Response Time-out Control CSR
6.2.1.4. Port General Control CSR
6.2.1.5. Port 0 Link Maintenance Request CSR
6.2.1.6. Port 0 Link Maintenance Response CSR
6.2.1.7. Port 0 Local AckID CSR
6.2.1.8. Port 0 Control 2 CSR
6.2.1.9. Port 0 Error and Status CSR
6.2.1.10. Port 0 Control CSR
6.3.1.1. CAR Memory Map
6.3.1.2. Device Identity CAR
6.3.1.3. Device Information CAR
6.3.1.4. Assembly Identity CAR
6.3.1.5. Assembly Information CAR
6.3.1.6. Processing Element Features CAR
6.3.1.7. Switch Port Information CAR
6.3.1.8. Source Operations CAR
6.3.1.9. Destination Operations CAR
6.3.1.10. Switch Route Table Destination ID Limit CAR
6.3.1.11. Data Streaming Information CAR
6.3.2.1. CSR Memory Map
6.3.2.2. Data Streaming Logical Layer Control CSR
6.3.2.3. Processing Element Logical Layer Control CSR
6.3.2.4. Local Configuration Space Base Address 0 CSR
6.3.2.5. Local Configuration Space Base Address 1 CSR
6.3.2.6. Base Device ID CSR
6.3.2.7. Host Base Device ID Lock CSR
6.3.2.8. Component Tag CSR
6.3.6.1. Error Management Extensions Extended Features Block Memory Map
6.3.6.2. Error Management Extensions Block Header
6.3.6.3. Logical/Transport Layer Error Detect
6.3.6.4. Logical/Transport Layer Error Enable
6.3.6.5. Logical/Transport Layer Address Capture
6.3.6.6. Logical/Transport Layer Device ID Capture
6.3.6.7. Logical/Transport Layer Control Capture
6.3.6.8. Port-Write Target Device ID
6.3.6.9. Packet Time-to-Live
6.3.6.10. Port 0 Error Detect
6.3.6.11. Port 0 Error Rate Enable
6.3.6.12. Port 0 Attributes Capture
6.3.6.13. Port 0 Packet/Control Symbol Capture 0
6.3.6.14. Port 0 Packet Capture 1
6.3.6.15. Port 0 Packet Capture 2
6.3.6.16. Port 0 Packet Capture 3
6.3.6.17. Port 0 Error Rate
6.3.6.18. Port 0 Error Rate Threshold
7.2.1. Reset, Initialization, and Configuration
7.2.2. Maintenance Write and Read Transactions
7.2.3. SWRITE Transactions
7.2.4. NREAD Transactions
7.2.5. NWRITE_R Transactions
7.2.6. NWRITE Transactions
7.2.7. Doorbell Transactions
7.2.8. Port-Write Transactions
7.2.9. Transactions Across the AVST Pass-Through Interface
2.7.5. External Transceiver PLL
RapidIO II IP cores that target an Intel® Arria® 10, Intel® Stratix® 10, or Intel® Cyclone® 10 GX device require an external TX transceiver PLL to compile and to function correctly in hardware. You must instantiate and connect this IP core to the RapidIO II IP core.
You can create an external transceiver PLL from the IP Catalog. Select the ATX PLL IP core or the fPLL IP core. In the PLL parameter editor, set the following parameter values:
- Set PLL output frequency to one half the value you select for the Maximum baud rate parameter in the RapidIO II parameter editor. The transceiver performs dual edge clocking, using both the rising and falling edges of the input clock from the PLL. Therefore, this PLL output frequency setting supports the customer-selected maximum data rate on the RapidIO link.
- Set PLL reference clock frequency to the value you select for the Reference clock frequency parameter in the RapidIO II parameter editor.
- Turn on Include Master Clock Generation Block.
- Turn on Enable bonding clock output ports.
- Set PMA interface width to 20.
<your_ip>/altera_rapidio2_<version>/synth/<your_ip>_altera_rapidio2_<version>_<random_string>.v/.vhd 6
However, the HDL code for the RapidIO II IP core does not instantiate the ATX PLL. If you choose to use the ATX PLL provided with the RapidIO II IP core, you must instantiate and connect the ATX PLL instance with the RapidIO II IP core in user logic.
Signal | Direction | Connection Requirements |
---|---|---|
pll_refclk0 | Input | Drive the PLL pll_refclk0 input port and the RapidIO II IP core tx_pll_refclk signal from the same clock source. The minimum allowed frequency for the pll_refclk0 clock in the Intel® Arria® 10 ATX PLL is 100 MHz. |
tx_bonding_clocks [(6 x < number of lanes >)–1:0] | Output | Connect tx_bonding_clocks[6n+5:6n] to the tx_bonding_clocks_chN input bus of transceiver channel N, for each transceiver channel N that connects to the RapidIO link. The transceiver channel input ports are RapidIO II IP core input ports. |
6 For Intel® Arria® 10 and Intel® Stratix® 10 devices, please refer to <your_ip>_generation.rpt file to get the filename for ATX PLL HDL code, listed in the line: atx_pll_wrapper_name: <atx pll name> .