RapidIO II Intel® FPGA IP User Guide

ID 683444
Date 9/28/2020
Public
Document Table of Contents

6.3.6.3. Logical/Transport Layer Error Detect

Table 155.  Logical/Transport Layer Error Detect CSR — Offset: 0x308
Field Bits Access Function Default
IO_ERROR_RSP 43 [31] RO Received a response of ERROR for an I/O Logical Layer Request. Set when the RapidIO II IP core detects this situation or when the io_error_response_set input signal changes value from 0 to 1. 1'b0
MSG_ERROR_RESPONSE 43 [30] RO Received a response of ERROR for a MSG Logical Layer Request. Set when the RapidIO II IP core detects this situation or when the message_error_response_set input signal changes value from 0 to 1. 1'b0
GSM_ERROR_RESPONSE 43 [29] RO Received a response of ERROR for a GSM Logical Layer Request. Set when the RapidIO II IP core detects this situation or when the gsm_error_response_set input signal changes value from 0 to 1. 1'b0
MSG_FORMAT_ERROR 43 [28] RO Received MESSAGE packet data payload with an invalid size or segment. Set when the RapidIO II IP core detects this situation or when the message_format_error_response_set input signal changes value from 0 to 1. 1'b0
ILL_TRAN_DECODE [27] RO Received illegal fields in the request/response packet for a supported transaction. Set when the RapidIO II IP core detects this situation or when the illegal_transaction_decode_set input signal changes value from 0 to 1. 1'b0
ILL_TRAN_TARGET [26] RO Received a packet that contained a destination ID that is not defined for this end point. Set when the RapidIO II IP core detects this situation or when the illegal_transaction_target_error_set input signal changes value from 0 to 1. An endpoint with multiple ports and a built-in switch function might not report this situation as an error. 1'b0
MSG_REQ_TIMEOUT 43 [25] RO A required message request has not been received within the specified time-out interval. Set when the message_request_timeout_set input signal changes value from 0 to 1. 1'b0
PKT_RSP_TIMEOUT 43 [24] RO A required response has not been received within the specified time-out interval. Set when the RapidIO II IP core detects this situation or when the slave_packet_response_timeout_set input signal changes value from 0 to 1. 1'b0
UNSOLICIT_RSP [23] RO Received an unsolicited or unexpected response packet (I/O, message, or GSM logical for endpoints; Maintenance for switches). Set when the RapidIO II IP core detects this situation or when the unsolicited_response_set input signal changes value from 0 to 1. 1'b0
UNSUPPORT_TRAN [22] RO Received a transaction that is not supported in the Destination Operations CAR. Set when the RapidIO II IP core detects this situation or when the unsupported_transaction_set input signal changes value from 0 to 1. 1'b0
MISSING_DATA_STRM_ CNTXT 43 [21] RO Received a continuation or end data streaming segment for a closed or non-existent segmentation context. Set when the missing_data_streaming_context_set input signal changes value from 0 to 1. 1'b0
OPEN_EXSTG_DATA_STRM_ CNTXT 43 [20] RO Received an initial or single data streaming segment for an already-open segmentation context. Set when the open_existing_data_streaming_context_set input signal changes value from 0 to 1. 1'b0
LONG_DATA_STRM_SGMNT 43 [19] RO Received a data streaming segment with a payload size greater than the MTU. Set when the long_data_streaming_segment_set input signal changes value from 0 to 1. 1'b0
SHRT_DATA_STRM_SGMNT 43 [18] RO Received a non-final data streaming segment with a payload size less than the MTU. Set when the short_data_streaming_segment_set input signal changes value from 0 to 1. 1'b0
DS_PDU_LEN_ERR 43 [17] RO The length of a reassembled PDU differs from the PDU length specified in the end data streaming segment packet header. Set when the data_streaming_pdu_length_error_set input signal changes value from 0 to 1. 1'b0
RSRV [16:8] RO Reserved. 9’h0
Implementation Specific error [7:0] RO This feature is not supported. 8’h00
Note: To clear bits in the Logical/Transport Layer Error Detect CSR, write the value of 32’h0000 to the register. You cannot clear the bits individually.
43 This error is registered for endpoint devices only.

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