RapidIO II Intel® FPGA IP User Guide

ID 683444
Date 9/28/2020
Public
Document Table of Contents

4.3.5.3.4. User Receiving Read Request and Sending Read Response

Table 46.   Avalon® -ST Pass-Through Interface Usage Example: Receiving NREAD Request and Sending Response
User Operation Operation Type RapidIO Transaction Priority Device ID Width Payload Size (Bytes)
Receive read request Rx NREAD 1 16 32
Send read response Tx Response with payload 2 16 32
The behavior of the signals on the Avalon® -ST pass-through interface for this example transaction sequence is described in
  • NREAD Request Transaction
  • NREAD Response Transaction
NREAD Request Transaction
The NREAD request requires a single clock cycle. During this cycle, user logic asserts gen_rx_hd_ready to indicate it is ready to sample data. In the same cycle, the IP core asserts gen_rx_hd_valid. Because both gen_rx_hd_ready and gen_rx_hd_valid are asserted, the current cycle is an Avalon® -ST ready cycle on the header Avalon® -ST interface. The IP core provides valid header information on gen_rx_hd_data for the user logic to sample.
Figure 32.  Avalon® -ST Pass-Through Interface NREAD Request Receive and Response Send Example
The IP core does not assert gen_rx_pd_valid, because the NREAD request transaction contains no payload data.
Table 47.  NREAD Request Receive Example: RapidIO Header Fields in gen_rx_hd_data Bus
Field gen_rx_hd_data Bits Value Comment
pd_size[8:0] [114:106] 9’h000 An NREAD request transaction has no payload data.
VC [105] 0 The RapidIO II IP core supports only VC0.
CRF [104] 0 This bit sets packet priority together with prio if CRF is supported. This bit is reserved if VC=0 and CRF is not supported.
prio[1:0] [103:102] 2'b01 Specifies packet priority.
tt[1:0] [101:100] 2'b01 The value of 1 indicates 16-bit device IDs.
ftype[3:0] [99:96] 4'b0010 The value of 2 indicates a Request Class packet.
destinationId[15:0] [95:80] 16’h00DD Indicates the ID of the target.
sourceId[15:0] [79:64] 16'h00AA Indicates the ID of the source.
ttype[3:0] [63:60] 4'b0100 The value of 4 indicates an NREAD transaction.
size[3:0] [59:56] 4'b1100 The size and wdptr values encode the maximum size of the payload field. In this example, they decode to a value of 32 bytes.
transactionID[7:0] [55:48] 8'hBB Value in the response packet matches the transactionID of the corresponding request packet.
address[28:0] [47:19] {28’h7654321, 1’b0}  
wdptr [18] 0 The size and wdptr values encode the maximum size of the payload field.
xamsbs[1:0] [17:16] 2’b00 Specifies most significant bits of extended address. Further extends the address specified by the address fields by 2 bits.
Reserved[15:0] [15:0] 16’h0000  
NREAD Response Transaction
In the first clock cycle of the NREAD response on the Avalon® -ST pass-through interface, the IP core asserts gen_tx_ready to indicate it is ready to sample data. In the same cycle, user logic asserts gen_tx_valid. Because both gen_tx_ready and gen_tx_valid are asserted, this clock cycle is an Avalon® -ST ready cycle. The user logic provides valid data on gen_tx_data for the IP core to sample, and asserts gen_tx_startofpacket to indicate the current value of gen_tx_data is the initial piece of the current packet (the start of packet). On gen_tx_packet_size, user logic reports the full length of the packet is 0x28, which is decimal 40, because the packet comprises eight bytes of header and 32 bytes of payload data.
Figure 33.  Avalon® -ST Pass-Through Interface NREAD Request Receive and Response Send Example
The user logic provides the 32-byte payload and 8-byte header on the same bus, gen_tx_data[127:0]. Transferring these 40 bytes of information requires three clock cycles. During all of these cycles, the IP core holds gen_tx_ready high and user logic holds gen_tx_valid high, indicating the cycles are all Avalon® -ST ready cycles. In the second cycle, user logic holds gen_tx_startofpacket and gen_tx_endofpacket low, because the information on gen_tx_data is neither start of packet nor end of packet data. In the third clock cycle, user logic asserts gen_tx_endofpacket and sets gen_tx_empty to the value of 0x8 to indicate that eight bytes of the data in the current clock cycle are invalid — in other words, only the initial eight (sixteen minus eight) bytes of data available on gen_tx_data in the current clock cycle are valid. The initial eight bytes of the NREAD response packet contain header information.
Table 48.  NREAD Response Transmit Example: RapidIO Header Fields on the gen_tx_data Bus
Field gen_tx_data Bits Value Comment
ackID [127:122] 6'h00 Value is a don’t care, because it is overwritten by the Physical layer ackID value before the packet is transmitted on the RapidIO link.
VC [121] 0 The RapidIO II IP core supports only VC0.
CRF [120] 0 This bit sets packet priority together with prio if CRF is supported. This bit is reserved if VC=0 and CRF is not supported.
prio[1:0] [119:118] 2'b10 Priority of the response packet. Value must be higher than the priority value of the request packet. In this example, the response packet has a priority value of 2’b10 and the original request has a priority value of 2’b01.
tt[1:0] [117:116] 2'b01 The value of 1 indicates 16-bit device IDs.
ftype[3:0] [115:112] 4’b1101 The value of 4’hD (decimal 13) indicates a Response Class packet.
destinationId[15:0] [111:96] 16'hDDDD The destinationID of the NREAD request are swapped in the response transaction.
sourceId[15:0] [95:80] 16'hAAAA The sourceID of the NREAD request are swapped in the response transaction.
ttype[3:0] [79:76] 4'b1000 The value of 8 indicates a Response transaction with data payload.
status[3:0] [75:72] 4'b0000 The value of 0 indicates Done. The current packet successfully completes the requested transaction.
transactionID[7:0] [71:64] 8'hBB Value in the response packet matches the transactionID of the corresponding request packet.

Did you find the information on this page useful?

Characters remaining:

Feedback Message