RapidIO II Intel® FPGA IP User Guide

ID 683444
Date 9/28/2020
Public
Document Table of Contents

5.2.3. Transceiver Signals

Table 59.  Transceiver SignalsThese signals are connected directly to the transceiver block. In some cases these signals must be shared by multiple transceiver blocks that are implemented in the same device.
Signal Direction Description
reconfig_to_xcvr Input Driven from an external dynamic reconfiguration block. Supports the selection of multiple transceiver channels for dynamic reconfiguration. Note that not using a dynamic reconfiguration block that enables offset cancellation results in a non-functional hardware design.

The width of this bus is (C + 1) × 70, where C is the number of channels: 1, 2, or 4. This width supports communication from the Reconfiguration Controller with C + 1 reconfiguration interfaces—one dedicated to each channel and another for the transceiver PLL—to the transceiver.

If you omit the Reconfiguration Controller from your simulation model, you must ensure all bits of this bus are tied to 0.

This bus is available only in Arria® V, Arria® V GZ, Cyclone® V, and Stratix® V IP core variations.
reconfig_from_xcvr Output Driven to an external dynamic reconfiguration block. The bus identifies the transceiver channel whose settings are being transmitted to the dynamic reconfiguration block. If no external dynamic reconfiguration block is used, then this output bus can be left unconnected.

The width of this bus is (C + 1) × 46, where C is the number of channels: 1, 2, or 4. This width supports communication from the transceiver to C + 1 reconfiguration interfaces in the Reconfiguration Controller, one interface dedicated to each channel and an additional interface for the transceiver PLL.

This bus is available only in Arria® V, Arria® V GZ, Cyclone® V, and Stratix® V IP core variations.
tx_cal_busy[n:0] Output Connect to the corresponding signal in the Transceiver PHY Reset Controller IP core, which implements the appropriate reset sequence for the device.
rx_cal_busy[n:0] Output Connect to the corresponding signal in the Transceiver PHY Reset Controller IP core, which implements the appropriate reset sequence for the device.
pll_locked Output Connect to the corresponding signal in the Transceiver PHY Reset Controller IP core, which implements the appropriate reset sequence for the device. This signal is available only in Arria® V, Arria® V GZ, Cyclone® V, and Stratix® V IP core variations.
pll_powerdown Input Connect to the corresponding signal in the Transceiver PHY Reset Controller IP core, which implements the appropriate reset sequence for the device. This signal is available only in Arria® V, Arria® V GZ, Cyclone® V, and Stratix® V IP core variations.
rx_digitalreset[n:0] Input Connect to the corresponding signal in the Transceiver PHY Reset Controller IP core, which implements the appropriate reset sequence for the device.
rx_digitalreset_stat[n:0] Output Connect to the corresponding signal in the Transceiver PHY Reset Controller IP core while using Intel® Stratix® 10 devices, which implements the appropriate reset sequence for the device.
rx_analogreset[n:0] Input Connect to the corresponding signal in the Transceiver PHY Reset Controller IP core, which implements the appropriate reset sequence for the device.
rx_analogreset_stat[n:0] Output Connect to the corresponding signal in the Transceiver PHY Reset Controller IP core while using Intel® Stratix® 10 devices, which implements the appropriate reset sequence for the device.
rx_ready[n:0 Input Connect to the corresponding signal in the Transceiver PHY Reset Controller IP core, which implements the appropriate reset sequence for the device.
tx_digitalreset[n:0] Input Connect to the corresponding signal in the Transceiver PHY Reset Controller IP core, which implements the appropriate reset sequence for the device.
tx_digitalreset_stat[n:0] Output Connect to the corresponding signal in the Transceiver PHY Reset Controller IP core while using Intel® Stratix® 10 devices, which implements the appropriate reset sequence for the device.
tx_analogreset[n:0] Input Connect to the corresponding signal in the Transceiver PHY Reset Controller IP core, which implements the appropriate reset sequence for the device.
tx_analogreset_stat[n:0] Output Connect to the corresponding signal in the Transceiver PHY Reset Controller IP core while using Intel® Stratix® 10 devices, which implements the appropriate reset sequence for the device.
tx_ready[n:0] Input Connect to the corresponding signal in the Transceiver PHY Reset Controller IP core, which implements the appropriate reset sequence for the device.
rx_is_lockedtodata[n:0] Output Connect to the corresponding signal in the Transceiver PHY Reset Controller IP core, which implements the appropriate reset sequence for the device.
rx_is_lockedtoref[n:0] Output Indicates that the CDR is locked to tx_pll_refclk.
rx_syncstatus[n:0] Output Indicates that the word aligner is synchronized to incoming data.
rx_signaldetect[n:0] Output Indicates that the lane detects a sender at the other end of the link: the signal is above the programmed signal detection threshold value.
Table 60.   Intel® Arria® 10, Intel® Stratix® 10 and Intel® Cyclone® 10 GX Transceiver Dynamic Reconfiguration Avalon® -MM Interface SignalsEach of these individual interfaces is an Avalon® -MM interface you use to access the hard PCS registers for the corresponding transceiver channel on the Intel® Arria® 10, Intel® Stratix® 10 and Intel® Cyclone® 10 GX devices. These signals are available if you turn on Enable transceiver dynamic reconfiguration in the RapidIO II parameter editor.
Signal Direction Description
reconfig_clk_ch0 Input Dynamic reconfiguration interface clock for the transceiver channel configured for RapidIO lane 0.
reconfig_reset_ch0 Input Dynamic reconfiguration interface reset for the transceiver channel configured for RapidIO lane 0.
reconfig_waitrequest_ch0 Output Dynamic reconfiguration slave wait request for the transceiver channel configured for RapidIO lane 0. The RapidIO II IP core uses this signal to stall the requestor on the interconnect.
reconfig_read_ch0 Input Dynamic reconfiguration slave read request for the transceiver channel configured for RapidIO lane 0.
reconfig_write_ch0 Input Dynamic reconfiguration slave write request for the transceiver channel configured for RapidIO lane 0.
reconfig_address_ch0[9:0] Input Dynamic reconfiguration slave address bus for the transceiver channel configured for RapidIO lane 0. The address is a word address, not a byte address.
reconfig_writedata_ch0[31:0] Input Dynamic reconfiguration slave write data bus for the transceiver channel configured for RapidIO lane 0.
reconfig_readdata_ch0[31:0] Output Dynamic reconfiguration slave read data bus for the transceiver channel configured for RapidIO lane 0.
reconfig_clk_ch1 Input Dynamic reconfiguration interface clock for the transceiver channel configured for RapidIO lane 1. This signal is available only in 2x and 4x variations.
reconfig_reset_ch1 Input Dynamic reconfiguration interface reset for the transceiver channel configured for RapidIO lane 1. This signal is available only in 2x and 4x variations.
reconfig_waitrequest_ch1 Output Dynamic reconfiguration slave wait request for the transceiver channel configured for RapidIO lane 1. The RapidIO II IP core uses this signal to stall the requestor on the interconnect. This signal is available only in 2x and 4x variations.
reconfig_read_ch1 Input Dynamic reconfiguration slave read request for the transceiver channel configured for RapidIO lane 1. This signal is available only in 2x and 4x variations.
reconfig_write_ch1 Input Dynamic reconfiguration slave write request for the transceiver channel configured for RapidIO lane 1. This signal is available only in 2x and 4x variations.
reconfig_address_ch1[9:0] Input Dynamic reconfiguration slave address bus for the transceiver channel configured for RapidIO lane 1. The address is a word address, not a byte address. This signal is available only in 2x and 4x variations.
reconfig_writedata_ch1[31:0] Input Dynamic reconfiguration slave write data bus for the transceiver channel configured for RapidIO lane 1. This signal is available only in 2x and 4x variations.
reconfig_readdata_ch1[31:0] Output Dynamic reconfiguration slave read data bus for the transceiver channel configured for RapidIO lane 1. This signal is available only in 2x and 4x variations.
reconfig_clk_ch2 Input Dynamic reconfiguration interface clock for the transceiver channel configured for RapidIO lane 2. This signal is available only in 4x variations.
reconfig_reset_ch2 Input Dynamic reconfiguration interface reset for the transceiver channel configured for RapidIO lane 2. This signal is available only in 4x variations.
reconfig_waitrequest_ch2 Output Dynamic reconfiguration slave wait request for the transceiver channel configured for RapidIO lane 2. The RapidIO II IP core uses this signal to stall the requestor on the interconnect. This signal is available only in 4x variations.
reconfig_read_ch2 Input Dynamic reconfiguration slave read request for the transceiver channel configured for RapidIO lane 2. This signal is available only in 4x variations.
reconfig_write_ch2 Input Dynamic reconfiguration slave write request for the transceiver channel configured for RapidIO lane 2. This signal is available only in 4x variations.
reconfig_address_ch2[9:0] Input Dynamic reconfiguration slave address bus for the transceiver channel configured for RapidIO lane 2. The address is a word address, not a byte address. This signal is available only in 4x variations.
reconfig_writedata_ch2[31:0] Input Dynamic reconfiguration slave write data bus for the transceiver channel configured for RapidIO lane 2. This signal is available only in 4x variations.
reconfig_readdata_ch2[31:0] Output Dynamic reconfiguration slave read data bus for the transceiver channel configured for RapidIO lane 2. This signal is available only in 4x variations.
reconfig_clk_ch3 Input Dynamic reconfiguration interface clock for the transceiver channel configured for RapidIO lane 3. This signal is available only in 4x variations.
reconfig_reset_ch3 Input Dynamic reconfiguration interface reset for the transceiver channel configured for RapidIO lane 3. This signal is available only in 4x variations.
reconfig_waitrequest_ch3 Output Dynamic reconfiguration slave wait request for the transceiver channel configured for RapidIO lane 3. The RapidIO II IP core uses this signal to stall the requestor on the interconnect. This signal is available only in 4x variations.
reconfig_read_ch3 Input Dynamic reconfiguration slave read request for the transceiver channel configured for RapidIO lane 3. This signal is available only in 4x variations.
reconfig_write_ch3 Input Dynamic reconfiguration slave write request for the transceiver channel configured for RapidIO lane 3. This signal is available only in 4x variations.
reconfig_address_ch3[9:0] Input Dynamic reconfiguration slave address bus for the transceiver channel configured for RapidIO lane 3. The address is a word address, not a byte address. This signal is available only in 4x variations.
reconfig_writedata_ch3[31:0] Input Dynamic reconfiguration slave write data bus for the transceiver channel configured for RapidIO lane 3. This signal is available only in 4x variations.
reconfig_readdata_ch3[31:0] Output Dynamic reconfiguration slave read data bus for the transceiver channel configured for RapidIO lane 3. This signal is available only in 4x variations
To control the transceivers, you must implement the following blocks in your design:
  • For Arria® V, Arria® V GZ, Cyclone® V, and Stratix® V variations: Dynamic reconfiguration block.
    The dynamic reconfiguration block lets you reconfigure the following PMA settings:
    • Pre-emphasis
    • Equalization
    • Offset cancellation
    • VOD on a per channel basis
  • For all variations: Reset controller block.

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