RapidIO II Intel® FPGA IP User Guide

ID 683444
Date 9/28/2020
Public
Document Table of Contents

6.2.1.3. Port Response Time-out Control CSR

Table 90.  Port Response Time-Out Control CSR — 0x124
Field Bits Access Function Default
VALUE [31:8] RW Time-out internal value for request-response pairs: the time interval between sending a request packet and receiving the corresponding response packet. The duration of the port response time-out for all transactions that require a response, including MAINTENANCE, DOORBELL, NWRITE_R, and NREAD transactions, is approximately equal to 4.5 seconds multiplied by the contents of this field, divided by (224 - 1).
Note:
  • A new value in this field might not propagate quickly enough to be applied to the next transaction.
  • Avoid changing the value in this field when any packet is waiting to be transmitted or waiting for a response, to ensure that in each FIFO, the pending entries all have the same time-out value.
24'hFF_FFFF
RSRV [7:0] UR0 Reserved. 8’h0

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