RapidIO II Intel® FPGA IP User Guide

ID 683444
Date 9/28/2020
Public
Document Table of Contents

4.2.2. Reference Clock

The reference clock, tx_pll_refclk, is the incoming reference clock for the transceiver’s PLL. You specify the reference clock frequency in the RapidIO II parameter editor when you create the RapidIO II IP core instance.

The ability to program the frequency of the input reference clock allows you to use an existing clock in your system as the reference clock for the RapidIO II IP core. This reference clock can have any of a set of frequencies that the PLL in the transceiver can convert to the required internal clock speed for the RapidIO II IP core baud rate. The choices available to you for this frequency are determined by the baud rate and target device family.
Note: You must drive the tx_pll_refclk clock from the same source from which you drive the sys_clk input clock and the TX PLL pll_refclk0 input clock. This source must be within ±100PPM of its nominal value, to ensure the difference between any two devices in the RapidIO II system is within ±200PPM.

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