RapidIO II Intel® FPGA IP User Guide

ID 683444
Date 9/28/2020
Public
Document Table of Contents

4.6.1. Physical Layer Error Management

Most errors at the Physical layer are categorized as:
  • Protocol violations
  • Transmission errors
Protocol violations can be caused by a link partner that is not fully compliant to the specification, or can be a side effect of the link partner being reset.
Transmission errors can be caused by noise on the line and consist of one or more bit errors. The following mechanisms exist for checking and detecting errors:
  • The receiver checks the validity of the received 8B10B encoded characters, including the running disparity.
  • The receiver detects control characters changed into data characters or data characters changed into control characters, based on the context in which the character is received.
  • The receiver checks the CRC of the received control symbols and packets.
The RapidIO II IP core Physical layer transparently manages these errors for you. The RapidIO specification defines both input and output error detection and recovery state machines that include handshaking protocols in which the receiving end signals that an error is detected by sending a packet-not-accepted control symbol, the transmitter then sends an input-status link-request control symbol to which the receiver responds with a link-response control symbol to indicate which packet requires transmission. The input and output error detection and recovery state machines can be monitored by software that you create to read the status of the Port 0 Error and Status CSR.

In addition to the registers defined by the specification, the RapidIO II IP core provides several output signals that enable user logic to monitor error detection and the recovery process.

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