RapidIO II Intel® FPGA IP User Guide

ID 683444
Date 9/28/2020
Public
Document Table of Contents

6.3.2.5. Local Configuration Space Base Address 1 CSR

Table 120.  Local Configuration Space Base Address 1 CSR — Offset: 0x5C
Field Bits Access Function Default
LCSBA [31] RO Reserved for a 34-bit local physical address. 1'b0
LCSBA [30:0] RW Bits [33:4] of a 34-bit physical address. 31'b0
Note: This register holds the local physical address double-word offset of the processing element’s configuration register space. If the Input/Output Avalon-MM master interface is connected to the Register Access Avalon-MM slave interface then regular read and write operations, rather than MAINTENANCE operations, can be used to access the processing element's registers for configuration and maintenance, based on this address. User logic must write the correct offset value in this register to ensure that these read and write operations can work correctly.

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