RapidIO II Intel® FPGA IP User Guide

ID 683444
Date 9/28/2020
Public
Document Table of Contents

4.3.4.3. Generating a Doorbell Message

To generate a DOORBELL request packet on the RapidIO serial interface, follow these steps, using the set of Doorbell Message Registers:
  1. Optionally enable interrupts by writing the value 1 to the appropriate bit of the Doorbell Interrupt Enable register.
  2. Optionally enable confirmation of successful outbound messages by writing 1 to the COMPLETED bit of the Tx Doorbell Status Control register.
  3. Set up the PRIORITY field of the Tx Doorbell Control register.
  4. Write the Tx Doorbell register to set up the DESTINATION_ID and Information fields of the generated DOORBELL packet format.
Note: Before writing to the Tx Doorbell register you must be certain that the Doorbell module has available space to accept the write data. Ensuring sufficient space exists avoids a waitrequest signal assertion due to a full FIFO. When the waitrequest signal is asserted, you cannot perform other transactions on the DOORBELL Avalon-MM slave port until the current transaction is completed. You can determine the combined fill level of the staging FIFO and the Tx FIFO by reading the Tx Doorbell Status register. The total number of Doorbell messages stored in the staging FIFO and the Tx FIFO, together, is limited to 16 by the assertion of the drbell_s_waitrequest signal.

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