RapidIO II Intel® FPGA IP User Guide

ID 683444
Date 9/28/2020
Document Table of Contents

2.7.2. Transceiver PHY Reset Controller

You must add a Transceiver PHY Reset Controller IP core to your design, and connect it to the RapidIO II IP core reset signals. This block implements a reset sequence that resets the device transceivers correctly.

In the Transceiver PHY Reset Controller parameter editor, you must perform the following for compatibility with the RapidIO II IP core:
  • Select the Use separate RX reset per channel option.

When you generate a RapidIO II IP core that target an Intel® Arria® 10, Intel® Stratix® 10, or Intel® Cyclone® 10 GX device, the Intel® Quartus® Prime software generates the HDL code for the Transceiver PHY Reset Controller in the following file: <your_ip>/altera_rapidio2_<version>/synth/<your_ip>_altera_rapidio2_<version>_<random_string>.v/.vhd 5

5 For Intel® Arria® 10, Intel® Stratix® 10 and Intel® Cyclone® 10 GX devices, please refer to <your_ip>_generation.rpt file to get the filename for Transceiver PHY Reset Controller HDL code, listed in the line: phy_reset_controller_wrapper_name: <PHY Reset Controller name>

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