RapidIO II Intel® FPGA IP User Guide

ID 683444
Date 9/28/2020
Public
Document Table of Contents

7.2. Testbench Sequence

The RapidIO II IP core testbench resets the DUT and the sister_rio module and initiates a sequence of transactions on each Avalon-MM and Avalon-ST interface that is relevant to this RapidIO II IP core variation.

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