RapidIO II Intel® FPGA IP User Guide

ID 683444
Date 9/28/2020
Public
Document Table of Contents

5.4. Error Management Extension Signals

Following signals are added when you enable the Error Management Extensions registers in the RapidIO II parameter editor. All of these signals are clocked in the sys_clk clock domain.
Table 73.  Error Setting Signals
Signal27 Direction Description
io_error_response_set Input Support user logic in setting the corresponding fields in the Logical/Transport Layer Error Detect CSR at offset 0x308.
message_error_response_set Input Support user logic in setting the corresponding fields in the Logical/Transport Layer Error Detect CSR at offset 0x308.
gsm_error_response_set Input Support user logic in setting the corresponding fields in the Logical/Transport Layer Error Detect CSR at offset 0x308.
message_format_error_response_set Input Support user logic in setting the corresponding fields in the Logical/Transport Layer Error Detect CSR at offset 0x308.
illegal_transaction_decode_set Input Support user logic in setting the corresponding fields in the Logical/Transport Layer Error Detect CSR at offset 0x308.
illegal_transaction_target_error_ set Input Support user logic in setting the corresponding fields in the Logical/Transport Layer Error Detect CSR at offset 0x308.
message_request_timeout_set Input Support user logic in setting the corresponding fields in the Logical/Transport Layer Error Detect CSR at offset 0x308.
slave_packet_response_timeout_set Input Support user logic in setting the corresponding fields in the Logical/Transport Layer Error Detect CSR at offset 0x308.
unsolicited_response_set Input Support user logic in setting the corresponding fields in the Logical/Transport Layer Error Detect CSR at offset 0x308.
unsupported_transaction_set Input Support user logic in setting the corresponding fields in the Logical/Transport Layer Error Detect CSR at offset 0x308.
missing_data_streaming_context_ set Input Support user logic in setting the corresponding fields in the Logical/Transport Layer Error Detect CSR at offset 0x308.
open_existing_data_streaming_ context_set Input Support user logic in setting the corresponding fields in the Logical/Transport Layer Error Detect CSR at offset 0x308.
long_data_streaming_segment_set Input Support user logic in setting the corresponding fields in the Logical/Transport Layer Error Detect CSR at offset 0x308.
short_data_streaming_segment_set Input Support user logic in setting the corresponding fields in the Logical/Transport Layer Error Detect CSR at offset 0x308.
data_streaming_pdu_length_error_ set Input Support user logic in setting the corresponding fields in the Logical/Transport Layer Error Detect CSR at offset 0x308.
Table 74.  Capture Signals
Signal28 Direction Description
external_capture_destinationID_wr Input Support user logic in setting the corresponding fields in the Logical/Transport Layer Device ID Capture CSR at offset 0x308.
external_capture_destinationID_in [15:0] Input Support user logic in setting the corresponding fields in the Logical/Transport Layer Device ID Capture CSR at offset 0x308.
external_capture_sourceID_wr Input Support user logic in setting the corresponding fields in the Logical/Transport Layer Device ID Capture CSR at offset 0x308.
external_capture_sourceID_in [15:0] Input Support user logic in setting the corresponding fields in the Logical/Transport Layer Device ID Capture CSR at offset 0x308.
capture_ftype_wr Input Support user logic in setting the FTYPE field in the Logical/Transport Layer Control Capture CSR at offset 0x308
capture_ftype_in[3:0] Input Support user logic in setting the FTYPE field in the Logical/Transport Layer Control Capture CSR at offset 0x308
capture_ttype_wr Input Support user logic in setting the TTYPE field in the Logical/Transport Layer Control Capture CSR at offset 0x308
capture_ttype_in[3:0] Input Support user logic in setting the TTYPE field in the Logical/Transport Layer Control Capture CSR at offset 0x308
letter_wr Input Support user logic in setting bits [3:0] of the MSG_INFO field in the Logical/Transport Layer Control Capture CSR at offset 0x308. The two signal pairs write to distinct bits and can be written simultaneously.
letter_in[1:0] Input Support user logic in setting bits [3:0] of the MSG_INFO field in the Logical/Transport Layer Control Capture CSR at offset 0x308. The two signal pairs write to distinct bits and can be written simultaneously.
mbox_wr Input Support user logic in setting bits [3:0] of the MSG_INFO field in the Logical/Transport Layer Control Capture CSR at offset 0x308. The two signal pairs write to distinct bits and can be written simultaneously.
mbox_in[1:0] Input Support user logic in setting bits [3:0] of the MSG_INFO field in the Logical/Transport Layer Control Capture CSR at offset 0x308. The two signal pairs write to distinct bits and can be written simultaneously.
msgseg_wr Input Support user logic in setting bits [7:4] of the the MSG_INFO field in the Logical/Transport Layer Control Capture CSR at offset 0x308. The two signal pairs write to the same register bits.

The value of msgseg_wr is written to MSG_INFO[7:4] when msgseg_wr has the value of 1’b1, irrespective of the value of xmbox_wr.

msgseg_in[3:0] Input Support user logic in setting bits [7:4] of the the MSG_INFO field in the Logical/Transport Layer Control Capture CSR at offset 0x308. The two signal pairs write to the same register bits.
xmbox_wr Input Support user logic in setting bits [7:4] of the the MSG_INFO field in the Logical/Transport Layer Control Capture CSR at offset 0x308. The two signal pairs write to the same register bits.
xmbox_in[3:0] Input Support user logic in setting bits [7:4] of the the MSG_INFO field in the Logical/Transport Layer Control Capture CSR at offset 0x308. The two signal pairs write to the same register bits.

The value of xmbox_in is written to MSG_INFO[7:4] only when xmbox_wr has the value of 1’b1 and msgseg_wr has the value of 1’b0.

27 If your design does not use one or more of these signals, you should tie the unused signals low.
28
  • To write to the register field for any of these signal pairs, drive the value on the _in signal and then set the _wr signal to the value of 1’b1. When the _wr signal has the value of 1’b1, on the rising edge of sys_clk, the value of the _in signal is written directly to the register field.
  • To ensure the signals are captured as required by the Error Management Extensions block, you must assert the _wr signal for each of these signals at the same time you assert the relevant Error Setting Signal.

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